Now showing items 1-10 of 10

  • Architectural support for task dependence management with flexible software scheduling 

    Castillo, Emilio; Álvarez Martí, Lluc; Moreto Planas, Miquel; Casas, Marc; Vallejo, Enrique; Bosque, Jose L.; Beivide Palacio, Ramon; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The growing complexity of multi-core architectures has motivated a wide range of software mechanisms to improve the orchestration of parallel executions. Task parallelism has become a very attractive approach thanks to its ...
  • CATA: Criticality aware task acceleration for multicore processors 

    Castillo, Emilio; Moreto Planas, Miquel; Casas, Marc; Álvarez Martí, Lluc; Vallejo, Enrique; Chronaki, Kallia; Badia Sala, Rosa Maria; Bosque Orero, José Luis; Beivide Palacio, Julio Ramón; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Conference report
    Open Access
    Managing criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities ...
  • Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures 

    Álvarez Martí, Lluc; Vilanova, Lluís; Moreto Planas, Miquel; Casas, Marc; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Association for Computing Machinery (ACM), 2015)
    Conference report
    Open Access
    The increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a ...
  • Hardware-software coherence protocol for the coexistence of caches and local memories 

    Álvarez Martí, Lluc; Vilanova, Lluís; González Tallada, Marc; Martorell Bofill, Xavier; Navarro, Nacho; Ayguadé Parra, Eduard (2015-01-01)
    Article
    Open Access
    Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce ...
  • Reducing cache coherence traffic with a NUMA-aware runtime approach 

    Caheny, Paul; Álvarez Martí, Lluc; Derradji, Said; Valero Cortés, Mateo; Moreto Planas, Miquel; Casas Guix, Marc (2018-05)
    Article
    Open Access
    Cache Coherent NUMA (ccNUMA) architectures are a widespread paradigm due to the benefits they provide for scaling core count and memory capacity. Also, the flat memory address space they offer considerably improves ...
  • Runtime-assisted cache coherence deactivation in task parallel programs 

    Caheny, Paul; Álvarez Martí, Lluc; Valero Cortés, Mateo; Moreto Planas, Miquel; Casas, Marc (Association for Computing Machinery (ACM), 2018)
    Conference report
    Open Access
    With increasing core counts, the scalability of directory-based cache coherence has become a challenging problem. To reduce the area and power needs of the directory, recent proposals reduce its size by classifying data ...
  • Runtime-aware architectures 

    Casas Guix, Marc; Moreto Planas, Miquel; Álvarez Martí, Lluc; Castillo Villar, Emilio; Chasapis, Dimitrios; Hayes, Timothy; Jaulmes, Luc Etienne; Palomar Pérez, Óscar; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José; Valero Cortés, Mateo (Springer, 2015)
    Conference report
    Open Access
    In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ...
  • Runtime-guided management of scratchpad memories in multicore architectures 

    Álvarez Martí, Lluc; Moreto Planas, Miquel; Casas Guix, Marc; Castillo Villar, Emilio; Martorell Bofill, Xavier; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Conference report
    Open Access
    The increasing number of cores and the anticipated level of heterogeneity in upcoming multicore architectures cause important problems in traditional cache hierarchies. A good way to alleviate these problems is to add ...
  • Runtime-guided management of stacked DRAM memories in task parallel programs 

    Álvarez Martí, Lluc; Casas, Marc; Labarta Mancho, Jesús José; Ayguadé Parra, Eduard; Valero Cortés, Mateo; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2018)
    Conference report
    Open Access
    Stacked DRAM memories have become a reality in High-Performance Computing (HPC) architectures. These memories provide much higher bandwidth while consuming less power than traditional off-chip memories, but their limited ...
  • Teaching HPC systems and parallel programming with small-scale clusters 

    Álvarez Martí, Lluc; Ayguadé Parra, Eduard; Mantovani, Filippo (Institute of Electrical and Electronics Engineers (IEEE), 2019)
    Conference report
    Restricted access - publisher's policy
    In the last decades, the continuous proliferation of High-Performance Computing (HPC) systems and data centers has augmented the demand for expert HPC system designers, administrators, and programmers. For this reason, ...