Browsing by Author "Soria Pardos, Víctor"Més informació

Now showing items 1-6 of 6

    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moreto Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...

    • Characterization and modeling of atomic memory operations in arm based architectures 

      Soria Pardos, Víctor (Universitat Politècnica de Catalunya, 2022-01-26)
      Master thesis
      Restricted access - confidentiality agreement
      Covenantee:   Barcelona Supercomputing Center / Universidad de Zaragoza
      Efficient fine-grain synchronization is a classic computer architecture challenge that has been profusely addressed in the past. Load Link and Store Conditional (LL/SC) became one of the few solutions to this problem and ...

    • Characterization of HPC applications for ARM SIMD instructions 

      Soria Pardos, Víctor (Universitat Politècnica de Catalunya, 2019-07)
      Bachelor thesis
      Open Access
      Hoy en día, la mayoría de repertorios de instrucciones (ISA) incluyen instrucciones que procesan multiples datos en una única instruccion. Éstas instrucciones se utilizan para acelerar aplicaciones de alto rendimiento ...

    • DVINO: A RISC-V vector processor implemented in 65nm technology 

      Cabo Pitarch, Guillem; Candon, Gerard; Carril, Xavier; Doblas Font, Max; Dominguez de la Rocha, Marc; González Trejo, Alberto; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel Israel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Minervini Minervini, Francesco; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas, Narcis; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruíz Ramírez, Abraham Josafat; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Figueras Bagué, Roger; Fontova, Pau; Marimon Illana, Joan; Montabes, Víctor; Cristal Kestelman, Adrián; Hernández Luz, Carles; Moreto Planas, Miquel; Moll Echeto, Francisco de Borja; Palomar Pérez, Óscar; Rubio Sola, Jose Antonio; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference lecture
      Open Access
      This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ...

    • On the use of many-core Marvell ThunderX2 processor for HPC workloads 

      Soria Pardos, Víctor; Armejach Sanosa, Adrià; Suárez Gracía, Dario; Moreto Planas, Miquel (2021)
      Article
      Open Access
      Marvell’s ThunderX2 has been the first Arm-based processor with deployments in large-scale HPC production systems, challenging the dominance that x86 processors had in the last decades. While x86 processors and its software ...

    • Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI 

      Soria Pardos, Víctor; Doblas Font, Max; López Paradís, Guillem; Candón Arenas, Gerard; Rodas Quiroga, Narcís; Carril Gil, Xavier; Fontova Muste, Pau; Leyva Santes, Neiel Israel; Marco-Sola, Santiago; Moreto Planas, Miquel (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference report
      Open Access
      The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing ...