Now showing items 1-11 of 11

    • Parametric Failure Analysis of Embedded SRAMs using Fast & Accurate Dynamic Analysis 

      Vatajelu, Elena Ioana; Panagopoulos, Georgios; Roy, Kaushik; Figueras Pàmies, Joan (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
      Conference report
      Restricted access - publisher's policy
    • Power-aware voltage tuning for STT-MRAM reliability 

      Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Di Carlo, Stefano; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Restricted access - publisher's policy
      One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. ...
    • Process variability in sub-16nm bulk CMOS technology 

      Rubio Sola, Jose Antonio; Figueras Pàmies, Joan; Vatajelu, Elena Ioana; Canal Corretger, Ramon (2012-03-01)
      External research report
      Open Access
      The document is part of deliverable D3.6 of the TRAMS Project (EU FP7 248789), of public nature, and shows and justifies the levels of variability used in the research project for sub-18nm bulk CMOS technologies.
    • Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell 

      Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Renovell, Michel; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Restricted access - publisher's policy
      The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin- Transfer-Torque ...
    • Reliability estimation at block-level granularity of spin-transfer-torque MRAMs 

      Di Carlo, Stefano; Indaco, Marco; Prinetto, Paolo; Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2014)
      Conference report
      Restricted access - publisher's policy
      In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under ...
    • Robustness of SRAM to Power Supply Noise during Leakage Power Saving in DVS 

      Vatajelu, Elena Ioana; Renovell, Michel; Figueras Pàmies, Joan (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
      Conference report
      Restricted access - publisher's policy
    • SRAM cell stability metric under transient voltage noise 

      Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (2013-12-20)
      Article
      Restricted access - publisher's policy
    • SRAM stability metric under transient noise 

      Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (2012)
      Conference report
      Open Access
      ventional way to analyze the robustness of an SRAM bit cell is to quantify its immunity to static noise. The static immunity to disturbances like process and mi smatch variations, bulk noises, supply rings variations, ...
    • Statistical analysis of SRAM aarametric failure under supply voltage scaling 

      Vatajelu, Elena Ioana; Figueras Pàmies, Joan (IEEE Computer Society Publications, 2010)
      Conference report
      Restricted access - publisher's policy
    • STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations 

      Vatajelu, Elena Ioana; Rodríguez Montañés, Rosa; Indaco, Marco; Prinetto, Paolo; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Restricted access - publisher's policy
      The CMOS based memories are facing major issues with technology scaling, such as decreased reliability and increased leakage power. A point will be reached when the technology scaling issues will overweight the benefits. ...
    • Transient noise failures in SRAM cells: dynamic noise margin metric 

      Vatajelu, Elena Ioana; Gómez Pau, Álvaro; Renovell, Michel; Figueras Pàmies, Joan (IEEE Computer Society Publications, 2011)
      Conference report
      Restricted access - publisher's policy
      Current nanometric IC processes need to assess the robustness of memories under any possible source of disturbance: process and mismatch variations, bulk noises, supply rings variations, temperature changes, aging and ...