Now showing items 1-10 of 10

    • A new look at the conditions for the synthesis of speed-independent circuits 

      Pastor Llorens, Enric; Cortadella, Jordi; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 1995)
      Conference report
      Open Access
      This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ...
    • Automatic generation of synchronous test patterns for asynchronous circuits 

      Roig Mansilla, Oriol; Cortadella, Jordi; Peña Basurto, Marco Antonio; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 1997)
      Conference report
      Open Access
      This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ...
    • Checking signal transition graph implementability by symbolic bdd traversal 

      Kondratyev, Alex; Cortadella, Jordi; Kishinevsky, Michael; Pastor Llorens, Enric; Roig Mansilla, Oriol; Yakovlev, Alex (Institute of Electrical and Electronics Engineers (IEEE), 1995)
      Conference report
      Open Access
      This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification ...
    • Flujo de diseño asíncrono con la biblioteca DCVSL_LIB para ES2 ECPD10 

      Sintes, L; Escudero Acuña, Javier; Peña Basurto, Marco Antonio; Roig Mansilla, Oriol; Cortadella, Jordi; Carrabina Bordoll, Jordi (Omron, 1996)
      Conference report
      Open Access
      En el presente trabajo se pretende abordar la metodología a seguir durante el flujo de diseño de un circuito asíncrono orientado a prestaciones, utilizando la biblioteca DCVSL_LIB para aplicaciones asíncronas que hemos ...
    • Hierarchical gate-level verification of speed-independent circuits 

      Roig Mansilla, Oriol; Cortadella, Jordi; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 1995)
      Conference report
      Open Access
      This paper presents a method for the verification of speed-independent circuits. The main contribution is the reduction of the circuit to a set of complex gates that makes the verification time complexity depend only on ...
    • Petri net analysis using boolean manipulation 

      Pastor Llorens, Enric; Roig Mansilla, Oriol; Cortadella, Jordi; Badia Sala, Rosa Maria (Springer, 1994)
      Part of book or chapter of book
      Open Access
      This paper presents a novel analysis approach for bounded Petri nets. The net behavior is modeled by boolean functions, thus reducing reasoning about Petri nets to boolean calculation. The state explosion problem is managed ...
    • Structural methods for the synthesis of speed-independent circuits 

      Pastor Llorens, Enric; Cortadella, Jordi; Kondratyev, Alex; Roig Mansilla, Oriol (1998-11)
      Article
      Open Access
      Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally ...
    • Structural methods for the synthesis of speed-independent circuits 

      Pastor Llorens, Enric; Cortadella, Jordi; Kondratyev, Alex; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 1996)
      Conference report
      Open Access
      Most existing tools for the synthesis of asynchronous circuits from Signal Transition Graphs (STGs) derive the reachability graph for the calculation of logic equations. This paper presents novel methods exclusively based ...
    • Symbolic analysis of bounded Petri nets 

      Pastor Llorens, Enric; Cortadella, Jordi; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 2001-05)
      Article
      Open Access
      This paper presents a symbolic approach for the analysis of bounded Petri nets. The structure and behavior of the Petri net is symbolically modeled by using Boolean functions, thus reducing reasoning about Petri nets to ...
    • Verification of asynchronous circuits by BDD-based model checking of Petri nets 

      Roig Mansilla, Oriol; Cortadella, Jordi; Pastor Llorens, Enric (Springer, 1995)
      Conference report
      Open Access
      This paper presents a methodology for the verification of speed-independent asynchronous circuits against a Petri net specification. The technique is based on symbolic reachability analysis, modeling both the specification ...