Now showing items 1-2 of 2

    • Runtime assisted cache memory optimizations 

      Dimic, Vladimir (Universitat Politècnica de Catalunya, 2015-07-09)
      Master thesis
      Restricted access - confidentiality agreement
    • Runtime-assisted shared cache insertion policies based on re-reference intervals 

      Dimic, Vladimir; Moreto Planas, Miquel; Casas Guix, Marc; Valero Cortés, Mateo (Springer, 2017)
      Conference report
      Open Access
      Processor speed is improving at a faster rate than the speed of main memory, which makes memory accesses increasingly expensive. One way to solve this problem is to reduce miss ratio of the processor’s last level cache by ...