Exploració per altres contribucions "Cazorla Almeida, Francisco Javier"
Ara es mostren els items 1-20 de 25
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A Multi-core processor for hard real-time systems
(Universitat Politècnica de Catalunya, 2011-11-04)
Tesi
Accés obertThe increasing demand for new functionalities in current and future hard real-time embedded systems, like the ones deployed in automotive and avionics industries, is driving an increment in the performance required in ... -
CPU accounting in multi-threaded processors
(Universitat Politècnica de Catalunya, 2014-05-29)
Tesi
Accés obertIn recent years, multi-threaded processors have become more and more popular in industry in order to increase the system aggregated performance and per-application performance, overcoming the limitations imposed by the ... -
Development and certification of mixed-criticality embedded systems based on probabilistic timing analysis
(Universitat Politècnica de Catalunya, 2018-07-02)
Tesi
Accés obertAn increasing variety of emerging systems relentlessly replaces or augments the functionality of mechanical subsystems with embedded electronics. For quantity, complexity, and use, the safety of such subsystems is an ... -
Enabling caches in probabilistic timing analysis
(Universitat Politècnica de Catalunya, 2017-09-06)
Tesi
Accés obertHardware and software complexity of future critical real-time systems challenges the scalability of traditional timing analysis methods. Measurement-Based Probabilistic Timing Analysis (MBPTA) has recently emerged as an ... -
Enhancing timing analysis for COTS multicores for safety-related industry : a software approach
(Universitat Politècnica de Catalunya, 2018-11-15)
Tesi
Accés obertArtificial system interaction with the real environment is in general based on the deployment of properly coordinated sensors and actuators, establishing between them a “dynamic control-loop”. The time to close this ... -
Exploring average-case and probabilistic worst-case performance of time randomised caches and their associated overheads
(Universitat Politècnica de Catalunya, 2016-01)
Projecte Final de Màster Oficial
Accés obertIn this work we focus on the analysis of performance in the context of Probabilistic Timing Analysis (PTA) from different angles. First, we model and evaluate average performance of time-randomised caches used in the context ... -
Exploring coordinated software and hardware support for hardware resource allocation
(Universitat Politècnica de Catalunya, 2009-09-04)
Tesi
Accés obertMultithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, ... -
Heterogeneity-awareness in multithreaded multicore processors
(Universitat Politècnica de Catalunya, 2009-07-07)
Tesi
Accés obertDuring the last decades, Computer Architecture has experienced a great series of revolutionary changes. The increasing transistor count on a single chip has led to some of the main milestones in the field, from the release ... -
Improving cache Behavior in CMP architectures throug cache partitioning techniques
(Universitat Politècnica de Catalunya, 2010-03-19)
Tesi
Accés obertThe evolution of microprocessor design in the last few decades has changed significantly, moving from simple inorder single core architectures to superscalar and vector architectures in order to extract the maximum available ... -
Improving the effective use of multithreaded architectures : implications on compilation, thread assignment, and timing analysis
(Universitat Politècnica de Catalunya, 2013-07-19)
Tesi
Accés obertThis thesis presents cross-domain approaches that improve the effective use of multithreaded architectures. The contributions of the thesis can be classified in three groups. First, we propose several methods for thread ... -
Improving the efficiency of multicore systems through software and hardware cooperation
(Universitat Politècnica de Catalunya, 2016-10-20)
Tesi
Accés obertIncreasing processors' clock frequency has traditionally been one of the largest drivers of performance improvements for computing systems. In the first half of the 2000s, however, it became clear that continuing to increase ... -
Improving time predictability of shared hardware resources in real-time multicore systems : emphasis on the space domain
(Universitat Politècnica de Catalunya, 2016-07-18)
Tesi
Accés obertCritical Real-Time Embedded Systems (CRTES) follow a verification and validation process on the timing and functional correctness. This process includes the timing analysis that provides Worst-Case Execution Time (WCET) ... -
Isolation QoS Setups to Control Memory Contention on MPSoCs
(Universitat Politècnica de Catalunya, 2023-10-19)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Barcelona Supercomputing CenterIn critical systems such as avionics and automotive domains, ensuring timely task execution is crucial to prevent catastrophic situations. The increasing trend towards autonomous operation demands higher performance and ... -
Modelling and predicting extreme behavior in critical real-time systems with advanced statistics
(Universitat Politècnica de Catalunya, 2023-03-13)
Tesi
Accés obert(English) Critical Real-Time Embedded Systems (CRTES) are used in domains like transportation (e.g. avionics, automotive, space, and railway), healthcare, and industrial machinery. This subset of embedded systems requires ... -
Modelling Contention in Multicore Hardware Resources during Early Design Stages of Real-Time Systems
(Universitat Politècnica de Catalunya, 2016-07)
Projecte Final de Màster Oficial
Accés obertThis thesis presents a modelling approach for the timing behavior of real-time embedded systems in early design phases. The model focuses on multicore processors and it predicts the contention tasks suffer in the access ... -
On the analysis of the timing behaviour of time randomised caches
(Universitat Politècnica de Catalunya, 2016-07-07)
Projecte Final de Màster Oficial
Accés obertTime Randomised caches (TRc), which can be implemented at hardware level or with software means on conventional deterministic cache designs, have been proposed for real-time systems as key enablers for Probabilistic ... -
On the Impact of Heterogeneous NoC Bandwidth Allocation in the WCET of Applications
(Universitat Politècnica de Catalunya, 2018-04-16)
Projecte Final de Màster Oficial
Accés obert
Realitzat a/amb: Barcelona Supercomputing Center / Barcelona Supercomputing CenterThis thesis analyzes the potential of a Flexible Bandwidth Allocation (FBA) method for networks-on-chip (NoCs), which provides heterogeneous bandwidth distribution to improve the worst-case execution time (WCET) of parallel ... -
On the limits of probabilistic timing analysis
(Universitat Politècnica de Catalunya, 2019-12-18)
Tesi
Accés obertOver the last years, we are witnessing the steady and rapid growth of Critica! Real-Time Embedded Systems (CRTES) industries, such as automotive and aerospace. Many of the increasingly-complex CRTES' functionalities that ... -
Per-task energy metering and accounting in the multicore era
(Universitat Politècnica de Catalunya, 2016-05-26)
Tesi
Accés obertChip multi-core processors (CMPs) are the preferred processing platform across different domains such as data centers, real-time systems and mobile devices. In all those domains, energy is arguably the most expensive ... -
Practical strategies to monitor and control contention in shared resources of critical real-time embedded systems
(Universitat Politècnica de Catalunya, 2023-04-03)
Tesi
Accés obert(English) In the last decade performance needs in Critical Real-Time Embedded Systems (CRTES) domains like automotive, avionics, railway or space have been steadily on the rise due to the unprecedented computational power ...
