Now showing items 1-20 of 22

    • 8T SRAM Cell with Open Defects under Voltage and Timing Variations 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Castillo Muñoz, Raul (2011)
      Conference report
      Open Access
    • Backside polishing detector: a new protection against backside attacks 

      Manich Bou, Salvador; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Mujal Colell, Jordi; Hernández García, David (2015)
      Conference report
      Open Access
      Secure chips are in permanent risk of attacks. Physical attacks usually start removing part of the package and accessing the dice by different means: laser shots, electrical or electromagnetic probes, etc. Doing this ...
    • BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Conference report
      Restricted access - publisher's policy
      Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done ...
    • Defective Behaviour of an 8T SRAM Cell with Open Defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador; Figueras Pàmies, Joan; Di Carlo, Stefano; Prinetto, Paolo; Scionti, Alberto (2010)
      Conference report
      Restricted access - publisher's policy
    • Design and validation of a platform for electromagnetic fault injection 

      Balasch, Josep; Arumi Delgado, Daniel; Manich Bou, Salvador (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Open Access
      Security is acknowledged as one of the main challenges in the design and deployment of embedded circuits. Devices need to operate on-the-field safely and correctly, even when at physical reach of potential adversaries. One ...
    • Diagnosis of full open defects in interconnect lines with fan-out 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, C.; Kruseman, Bram (IEEE Press. Institute of Electrical and Electronics Engineers, 2010-05-24)
      Conference report
      Open Access
      The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes ...
    • Diagnosis of full open defects in interconnecting lines 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram; Lousberg, M.; Majhi, A.K. (IEEE, 2007-05-31)
      Conference report
      Open Access
      A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). ...
    • Gate leakage impact on full open defects in interconnect lines 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan; Eichenberger, Stefan; Hora, Camelia; Kruseman, Bram (2011-06)
      Article
      Open Access
      An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, ...
    • Impact of gate tunnelling leakage on CMOS circuits with full open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Eichenberger, S.; Hora, Camelia; Kruseman, B. (Institution of Electrical Engineers, 2007-10)
      Article
      Open Access
      Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered electrically isolated ...
    • Impact of laser attacks on the switching behavior of RRAM devices 

      Arumi Delgado, Daniel; Manich Bou, Salvador; Gómez Pau, Álvaro; Rodríguez Montañés, Rosa; Montilla, Víctor; Hernández, David; Bargalló González, Mireia; Campabadal, Francesca (2020-01-20)
      Article
      Open Access
      The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative ...
    • Localization and electrical characterization of interconnect open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan; Beverloo, Willem; Vries, Dirk K. de; Eichenberger, Stefan; Volf, Paul A. J. (2010-02)
      Article
      Open Access
      A technique for extracting the electrical and topological parameters of open defects in process monitor lines is presented. The procedure is based on frequency-domain measurements performed at both end points of the ...
    • Post-Bond test of through-silicon vias with open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan (2014)
      Conference report
      Restricted access - publisher's policy
      Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during ...
    • Postbond test of through-silicon vias with resistive open defects 

      Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Figueras Pàmies, Joan (2019-07-17)
      Article
      Open Access
      Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are ...
    • Prebond testing of weak defects in TSVs 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras Pàmies, Joan (2015-08-07)
      Article
      Restricted access - publisher's policy
      Through-silicon vias (TSVs) are critical elements in 3-D integrated circuits susceptible to defects during fabrication and lifetime. It is desirable to detect defective TSVs in the early steps of the fabrication process ...
    • Random masking interleaved scrambling technique as a countermeasure for DPA/DEMA attacks in cache memories 

      Neagu, Mădălin; Rodríguez Montañés, Rosa; Arumi Delgado, Daniel; Manich Bou, Salvador (2016-11-15)
      Conference report
      Open Access
      Memory remanence in SRAMs and DRAMs is usually exploited through cold-boot attacks and the targets are the main memory and the L2 cache memory. Hence, a sudden power shutdown may give an attacker the opportunity to ...
    • Resistive open defect characteritzation in 3D 6T SRAM memories 

      Castillo, Raúl; Arumi Delgado, Daniel; Rodríguez Montañés, Rosa (2014)
      Conference report
      Restricted access - publisher's policy
      The relentless decrease in feature size and the increase of density requirements in Integrated Circuit (IC) manufacturing arise new challenges that must be overcome. One of the most promising alternatives is three-dimensional ...
    • RRAM based cell for hardware security applications 

      Arumi Delgado, Daniel; Manich Bou, Salvador; Rodríguez Montañés, Rosa (2016)
      Conference report
      Restricted access - publisher's policy
      Resistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. ...
    • RRAM Based Random Bit Generation for Hardware Security Applications 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Manich Bou, Salvador; Pehl, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Resistive random access memories (RRAMs) have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end ...
    • RRAM serial configuration for the generation of random bits 

      Arumi Delgado, Daniel; Gonzalez, Mireia B.; Campabadal, Francesca (2017-06-25)
      Article
      Open Access
    • Test escapes of stuck-open faults caused by parasitic capacitances and leakage currents 

      Arumi Delgado, Daniel; Rodríguez Montañés, Rosa; Figueras, Joan (2015-09-24)
      Article
      Open Access
      Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled ...