Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2013-06-17)
Master thesis (pre-Bologna period)
Restricted access - confidentiality agreement
Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2020-01-24)
Open AccessWith the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of ...
Vidal Obiols, Alexandre; Cortadella, Jordi; Petit Silvestre, Jordi; Galcerán Oms, Marc; Martorell Cid, Ferran (Institute of Electrical and Electronics Engineers (IEEE), 2019)
Open AccessWhen RTL designers define the hierarchy of a system, they exploit their knowledge about the conceptual abstractions devised during the design and the functional interactions between the logical components. This valuable ...
Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2015-10-15)
Open AccessThis thesis presents the extension of a routing framework for the internal routing of standard cells. We extend the original Boolean formulation and modify a SAT-solver to take advantage of the new variables. Our aim is ...
Vidal Obiols, Alexandre; Cortadella, Jordi; Petit Silvestre, Jordi (Association for Computing Machinery (ACM), 2017)
Open AccessThe progressive miniaturization of technology and the unequal scalability of the BEOL and FEOL layers aggravate the routing congestion problem and have a negative impact on manufacturability. Standard cells are designed ...