Exploració per autor "Salami, Behzad"
Ara es mostren els items 1-20 de 24
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A Demo of FPGA Aggressive Voltage Downscaling: Power and Reliability Tradeoffs
(IEEE, 2018-12-06)
Comunicació de congrés
Accés obertThe power consumption of digital circuits, e.g., Field Programmable Gate Arrays (FPGAs), is directly related to their operating supply voltages. On the other hand, usually, chip vendors introduce a conservative voltage ... -
A novel FPGA-based high throughput accelerator for binary search trees
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertThis paper presents a deeply pipelined and massively parallel Binary Search Tree (BST) accelerator for Field Programmable Gate Arrays (FPGAs). Our design relies on the extremely parallel on-chip memory, or Block RAMs (BRAMs) ... -
Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique
(Springer International Publishing, 2017-04-29)
Comunicació de congrés
Accés obertExtracting valuable information from the rapidly growing field of Big Data faces serious performance constraints, especially in the software-based database management systems (DBMS). In a query processing system, hash-based ... -
Aggressive undervolting of FPGAs : power & reliability trade-offs
(Universitat Politècnica de Catalunya, 2018-11-19)
Tesi
Accés obertIn this work, we evaluate aggressive undervolting, i.e., voltage underscaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by ... -
An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertWe empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field ... -
AxleDB: A novel programmable query processing platform on FPGA
(Elsevier, 2017-06-01)
Article
Accés obertWith the rise of Big Data, providing high-performance query processing capabilities through the acceleration of the database analytic has gained significant attention. Leveraging Field Programmable Gate Array (FPGA) ... -
Can we trust undervolting in FPGA-based deep learning designs at harsh conditions?
(2022-05)
Article
Accés obertAs more Neural Networks on Field Programmable Gate Arrays (FPGAs) are used in a wider context, the importance of power efficiency increases. However, the focus on power should never compromise application accuracy. One ... -
Comprehensive Evaluation of Supply Voltage Underscaling in FPGA on-Chip Memories
(IEEE, 2018-12-13)
Comunicació de congrés
Accés obertIn this work, we evaluate aggressive undervolting, i.e., voltage scaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip ... -
Demonstrating reduced-voltage FPGA-based neural network acceleration for power-efficiency
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Comunicació de congrés
Accés obertThis demo aims to demonstrate undervolting below the nominal level set by the vendor for off-the-shelf FPGAs running Deep Neural Networks (DNNs), to achieve power-efficiency. FPGAs are becoming popular [1-4], thanks to ... -
Evaluating built-in ECC of FPGA on-chip memories for the mitigation of undervolting faults
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Text en actes de congrés
Accés obertVoltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage ... -
Exceeding conservative limits: A consolidated analysis on modern hardware margins
(2020-06)
Article
Accés obertModern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core ... -
Experimental study of aggressive undervolting in FPGAs
(Barcelona Supercomputing Center, 2019-05-07)
Text en actes de congrés
Accés obertIn this work, we evaluate aggressive undervolting, i.e., voltage scaling below the nominal level to reduce the energy consumption of Field Programmable Gate Arrays (FPGAs). Usually, voltage guardbands are added by chip ... -
Fault Characterization Through FPGA Undervolting
(IEEE, 2018-12-06)
Comunicació de congrés
Accés obertThe power and energy efficiency of Field Programmable Gate Arrays (FPGAs) are estimated to be up to 20X less than Application Specific Integrated Circuits (ASICs). What is needed to close this gap is aggressive power/energy ... -
Hardware acceleration for query processing: Leveraging FPGAs, CPUs, and memory
(2016-01)
Article
Accés obertDatabase management systems have become an indispensable tool for industry, government, and academia, and form a significant component of modern datacenters. They can be used in a multitude of scenarios, including online ... -
HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA
(Institute of Electrical and Electronics Engineers (IEEE), 2015-05)
Text en actes de congrés
Accés obertIn this paper we present HATCH, a novel hash join engine. We follow a new design point which enables us to effectively cache the hash table entries in fast BRAM resources, meanwhile supporting collision resolution in ... -
LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing
(ACM, 2018-07-15)
Comunicació de congrés
Accés obertLEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of ... -
LEGaTO: Low-energy, secure, and resilient toolset for heterogeneous computing
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertThe LEGaTO project leverages task-based programming models to provide a software ecosystem for Made in-Europe heterogeneous hardware composed of CPUs, GPUs, FPGAs and dataflow engines. The aim is to attain one order of ... -
LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing
(Association for Computing Machinery (ACM), 2018-05-08)
Comunicació de congrés
Accés obertLEGaTO is a three-year EU H2020 project which started in December 2017. The LEGaTO project will leverage task-based programming models to provide a software ecosystem for Made-in-Europe heterogeneous hardware composed of ... -
Leveraging FPGAs to accelerate the query processing of SQL-based databases
(Barcelona Supercomputing Center, 2017-05-04)
Text en actes de congrés
Accés obert -
MoRS: An approximate fault modelling framework for reduced-voltage SRAMs
(2022-06)
Article
Accés obertOn-chip memory (usually based on Static RAMs-SRAMs) are crucial components for various computing devices including heterogeneous devices, e.g, GPUs, FPGAs, ASICs to achieve high performance. Modern workloads such as Deep ...
