Now showing items 1-5 of 5

    • FastIC: a fast integrated circuit for the readout of high performance detectors 

      Gómez Fernández, Sergio; Alozy, J.; Campbell, Michael; Manera Escalero, Rafael; Mauricio Ferré, Juan; Sanmukh, Anand; Sanuy Charles, Andreu; Ballabriga, Rafael; Gascón Fora, David (2022-05-01)
      Article
      Restricted access - publisher's policy
      This work presents the 8-channel FastIC ASIC developed in CMOS 65¿nm technology suitable for the readout of positive and negative polarity sensors in high energy physics experiments, Cherenkov detectors and time-of-flight ...
    • Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations 

      Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja; Mauricio Ferré, Juan (2014-07-01)
      Article
      Open Access
      A lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables ...
    • Local variations compensation with DLL-based body bias generator for UTBB FD-SOI technology 

      Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Conference report
      Restricted access - publisher's policy
      Local variations are increasingly important in new technologies. This paper presents the design of adaptive circuits based on the concept of Adaptive Body Bias Islands and a Forward and Reverse Body Bias Generator for FDSOI ...
    • Measurements of process variability in 40-nm regular and nonregular layouts 

      Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Gómez Fernández, Sergio (2014-02-01)
      Article
      Restricted access - publisher's policy
      As technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ...
    • Monitor strategies for variability reduction considering correlation between power and timing variability 

      Mauricio Ferré, Juan; Moll Echeto, Francisco de Borja; Altet Sanahujes, Josep (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
      Conference report
      Restricted access - publisher's policy
      As CMOS technology scales, Process, Voltage and Temperature (PVT) variations have an increasing impact on, performance and power consumption of the electronic devices. Variability causes an undesirable dispersion of ...