Exploració per autor "Ramírez Lazo, Cristóbal"

Ara es mostren els items 1-8 de 8

    • A RISC-V simulator and benchmark suite for designing and evaluating vector architectures 

      Ramírez Lazo, Cristóbal; Hernández, César Alejandro; Palomar Pérez, Óscar; Unsal, Osman Sabri; Ramírez Salinas, Marco Antonio; Cristal Kestelman, Adrián (2020-11)
      Article
      Accés obert
      Vector architectures lack tools for research. Consider the gem5 simulator, which is possibly the leading platform for computer-system architecture research. Unfortunately, gem5 does not have an available distribution that ...

    • Adaptable register file organization for vector processors 

      Ramírez Lazo, Cristóbal (Universitat Politècnica de Catalunya, 2022-04-04)
      Tesi
      Accés obert
      Today there are two main vector processors design trends. On the one hand, we have vector processors designed for long vectors lengths such as the SX-Aurora TSUBASA which implements vector lengths of 256 elements (16384-bits). ...

    • Adaptable register file organization for vector processors 

      Ramírez Lazo, Cristóbal; Reggiani, Enrico; Rojas Morales, Carlos; Figueras Bagué, Roger; Villa Vargas, Luis Alfonso; Ramírez Salinas, Marco Antonio; Valero Cortés, Mateo; Unsal, Osman Sabri; Cristal Kestelman, Adrián (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Text en actes de congrés
      Accés obert
      Contemporary Vector Processors (VPs) are de-signed either for short vector lengths, e.g., Fujitsu A64FX with 512-bit ARM SVE vector support, or long vectors, e.g., NEC Aurora Tsubasa with 16Kbits Maximum Vector Length ...

    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Text en actes de congrés
      Accés obert
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...

    • BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge 

      Reggiani, Enrico; Ramírez Lazo, Cristóbal; Figueras Bagué, Roger; Cristal Kestelman, Adrián; Olivieri, Mauro; Unsal, Osman Sabri (Association for Computing Machinery (ACM), 2022)
      Comunicació de congrés
      Accés obert
      Linear algebra computational kernels based on byte and sub-byte integer data formats are at the base of many classes of applications, ranging from Deep Learning to Pattern Matching. Porting the computation of these ...

    • Design and implementation of an out of order execution engine of floating point arithmetic operations 

      Ramírez Lazo, Cristóbal (Universitat Politècnica de Catalunya, 2016-02-04)
      Projecte Final de Màster Oficial
      Accés obert
      Realitzat a/amb:   Instituto Politécnico Nacional. Centro de Investigación en Computación
      In this thesis, work is undertaken towards the design in hardware description languages and implementation in FPGA of an out of order execution engine of floating point arithmetic operations. This thesis work, is part of ...

    • DVINO: A RISC-V vector processor implemented in 65nm technology 

      Cabo Pitarch, Guillem; Candon, Gerard; Carril, Xavier; Doblas Font, Max; Dominguez de la Rocha, Marc; González Trejo, Alberto; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel Israel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Minervini Minervini, Francesco; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas, Narcis; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruíz Ramírez, Abraham Josafat; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Figueras Bagué, Roger; Fontova, Pau; Marimon Illana, Joan; Montabes, Víctor; Cristal Kestelman, Adrián; Hernández Luz, Carles; Moretó Planas, Miquel; Moll Echeto, Francisco de Borja; Palomar Pérez, Óscar; Rubio Sola, Jose Antonio; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Comunicació de congrés
      Accés obert
      This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ...

    • Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology 

      Doblas Font, Max; Candón Arenas, Gerard; Carril Gil, Xavier; Dominguez de la Rocha, Marc; Erra, Enric; González Trejo, Alberto; Jiménez, Víctor; Kostalampros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Mendoza Escobar, Jonnatan; Oltra Oltra, Josep Angel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Rodas Quiroga, Narcís; Reggiani, Enrico; Rodriguez, Mario; Rojas Morales, Carlos; Ruiz Ramirez, Abraham Josafat; Safadi Figueroa, Hugo Ernesto; Soria Pardos, Víctor; Vargas Valdivieso, Iván; Arreza, Fernando; Figueras Bagué, Roger; Fontova Muste, Pau; Marimon Illana, Joan; Aragonès Cervera, Xavier; Cristal Kestelman, Adrián; Mateo Peña, Diego; Moll Echeto, Francisco de Borja; Moretó Planas, Miquel; Palomar Pérez, Óscar; Sonmez, Nehir; Unsal, Osman Sabri; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
      Accés obert
      This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ...