Browsing by Author "Rubio Sola, Jose Antonio"
Now showing items 1-20 of 118
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1-D memristor networks as ternary storage cells
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Restricted access - publisher's policyDue to its inherent analog nature, the memristor can store information in a continuous form, being thus well-suited for compact multi-bit memory cell technology. In this context, threshold-type switching devices show great ... -
A comparative variability analysis for CMOS and CNFET 6T SRAM cells
(2011)
Conference report
Restricted access - publisher's policyStatistical device variability may be a limiting factor for further miniaturizing nodes in silicon bulk CMOS technology. On the other hand, in novel technologies such as Carbon Nanotubes Field Effect Transistors (CNFETs), ... -
A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits
(IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
Conference report
Open AccessAbstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits ... -
A crosstalk latch circuit design
(Institute of Electrical and Electronics Engineers (IEEE), 1990)
Conference report
Restricted access - publisher's policyA D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ... -
A digital memristor emulator for FPGA-based artificial neural networks
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Conference report
Restricted access - publisher's policyFPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain ... -
A new probabilistic design methodology of nanoscale digital circuits
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Conference report
Restricted access - publisher's policyThe continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ... -
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
(IEEE Computer Society Publications, 2012)
Conference report
Restricted access - publisher's policyIn view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ... -
A pragmatic gaze on stochastic resonance based variability tolerant memristance
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Open AccessStochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other ... -
A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture
(2014-05-05)
Article
Restricted access - publisher's policy -
A single event transient hardening circuit design technique based on strengthening
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyIn a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ... -
A systematic method to design efficient ternary high performance CNTFET-based logic cells
(Institute of Electrical and Electronics Engineers (IEEE), 2020-01-01)
Article
Open AccessThe huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to ... -
Active radiation-hardening strategy in bulk FinFETs
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Article
Open AccessIn this paper, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates ... -
Adaptive fault-tolerant architecture for unreliable device technologies
(CRC Press, Taylor and Francis Group, 2013-06-03)
Part of book or chapter of book
Restricted access - publisher's policyNanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ... -
Adaptive fault-tolerant architecture for unreliable device technologies
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Conference report
Restricted access - publisher's policyThis paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging ... -
Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability
(2012-07)
Article
Restricted access - publisher's policyThis paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ... -
Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design
(2014)
Article
Open AccessNanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive ... -
Advanced failure detection techniques in deep submicron CMOS integrated circuits
(Pergamon Press, 2009)
Conference report
Restricted access - publisher's policyThe test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ... -
An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
An on-line test strategy and analysis for a 1T1R crossbar memory
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Conference report
Open AccessMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ... -
Analysis and modelling of parasitic substrate coupling in CMOS circuits
(1995-10)
Article
Restricted access - publisher's policyAnalysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ...
