Exploració per autor "Rubio Sola, Jose Antonio"
Ara es mostren els items 1-20 de 108
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1-D memristor networks as ternary storage cells
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialDue to its inherent analog nature, the memristor can store information in a continuous form, being thus well-suited for compact multi-bit memory cell technology. In this context, threshold-type switching devices show great ... -
A comparative variability analysis for CMOS and CNFET 6T SRAM cells
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialStatistical device variability may be a limiting factor for further miniaturizing nodes in silicon bulk CMOS technology. On the other hand, in novel technologies such as Carbon Nanotubes Field Effect Transistors (CNFETs), ... -
A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits
(IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
Text en actes de congrés
Accés obertAbstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits ... -
A crosstalk latch circuit design
(Institute of Electrical and Electronics Engineers (IEEE), 1990)
Text en actes de congrés
Accés restringit per política de l'editorialA D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ... -
Adaptive fault-tolerant architecture for unreliable device technologies
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging ... -
Adaptive fault-tolerant architecture for unreliable device technologies
(CRC Press, Taylor and Francis Group, 2013-06-03)
Capítol de llibre
Accés restringit per política de l'editorialNanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ... -
Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability
(2012-07)
Article
Accés restringit per política de l'editorialThis paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ... -
Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design
(2014)
Article
Accés obertNanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive ... -
A digital memristor emulator for FPGA-based artificial neural networks
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialFPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain ... -
Advanced failure detection techniques in deep submicron CMOS integrated circuits
(Pergamon Press, 2009)
Text en actes de congrés
Accés restringit per política de l'editorialThe test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ... -
Análisis del retardo en enlaces con protocolos ARQ y control de flujo: aplicación a una red estrella
(Marcombo, 1983)
Text en actes de congrés
Accés obertEl objetivo de este trabajo se enmarca en el desarrollo de herramientas de cuantificación de los tiempos de retardo en redes de computadores. El análisis se ha centrado en la evaluación del tiempo medio de retardo en el ... -
Analysis and modelling of parasitic substrate coupling in CMOS circuits
(1995-10)
Article
Accés restringit per política de l'editorialAnalysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ... -
Analysis of body bias and RTN-induced frequency shift of low voltage ring oscillators in FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés restringit per política de l'editorialElectronic circuits powered at ultra low voltages (500 mV and below) are desirable for their low energy and power consumption. However, RTN (Random Telegraph Noise)-induced threshold voltage variations become very significant ... -
Analysis of delay mismatching of digital circuits caused by common environmental fluctuations
(IEEE, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialEnvironmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity ... -
A new probabilistic design methodology of nanoscale digital circuits
(IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
Text en actes de congrés
Accés restringit per política de l'editorialThe continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ... -
An on-line test strategy and analysis for a 1T1R crossbar memory
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertMemristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ... -
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
(IEEE Computer Society Publications, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIn view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ... -
A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture
(2014-05-05)
Article
Accés restringit per política de l'editorial -
A single event transient hardening circuit design technique based on strengthening
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialIn a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ... -
Asynchronous pulse logic cell for threshold logic and Boolean networks
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés restringit per política de l'editorialIn this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ...
