Now showing items 1-20 of 118

    • 1-D memristor networks as ternary storage cells 

      Vourkas, Ioannis; Abusleme, Angel; Sirakoulis, Georgios; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
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      Due to its inherent analog nature, the memristor can store information in a continuous form, being thus well-suited for compact multi-bit memory cell technology. In this context, threshold-type switching devices show great ...
    • A comparative variability analysis for CMOS and CNFET 6T SRAM cells 

      García Almudéver, Carmen; Rubio Sola, Jose Antonio (2011)
      Conference report
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      Statistical device variability may be a limiting factor for further miniaturizing nodes in silicon bulk CMOS technology. On the other hand, in novel technologies such as Carbon Nanotubes Field Effect Transistors (CNFETs), ...
    • A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits 

      Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
      Conference report
      Open Access
      Abstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits ...
    • A crosstalk latch circuit design 

      Rubio Sola, Jose Antonio; Pons Nin, Joan; Anglada, Raimon (Institute of Electrical and Electronics Engineers (IEEE), 1990)
      Conference report
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      A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range ...
    • A digital memristor emulator for FPGA-based artificial neural networks 

      Vourkas, Ioanis; Abusleme, A.; Ntinas, V.; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
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      FPGAs are reconfigurable electronic platforms, well-suited to implement complex artificial neural networks (ANNs). To this end, the compact hardware (HW) implementation of artificial synapses is an important step to obtain ...
    • A new probabilistic design methodology of nanoscale digital circuits 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
      Conference report
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      The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ...
    • A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Enrico; González Colás, Antonio María; Rubio Sola, Jose Antonio (IEEE Computer Society Publications, 2012)
      Conference report
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      In view of device scaling issues, embedded DRAM (eDRAM) technology is being considered as a strong alternative to conventional SRAM for use in on-chip memories. Memory cells designed using eDRAM technology in addition ...
    • A pragmatic gaze on stochastic resonance based variability tolerant memristance 

      Ntinas, Vasileios; Rubio Sola, Jose Antonio; Sirakoulis, Georgios Ch.; Cotofana, Sorin (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      Stochastic Resonance (SR) is a nonlinear system specific phenomenon, which was demonstrated to lead to system unexpected (counter-intuitive) performance improvements under certain noise conditions. Memristor, on the other ...
    • A shapeshifting evolvable hardware mechanism based on reconfigurable memFETs crossbar architecture 

      Martín Martínez, Javier; García Almudéver, Carmen; Crespo Yepes, Albert; Rodríguez Martínez, Rosana; Nafría Maqueda, Montserrat; Rubio Sola, Jose Antonio (2014-05-05)
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    • A single event transient hardening circuit design technique based on strengthening 

      Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Conference report
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      In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ...
    • A systematic method to design efficient ternary high performance CNTFET-based logic cells 

      Dabaghi Zarandi, Arezoo; Reza Reshadinezhad, Mohammad; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2020-01-01)
      Article
      Open Access
      The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to ...
    • Active radiation-hardening strategy in bulk FinFETs 

      Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Moll Echeto, Francisco de Borja; Gamiz, Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Article
      Open Access
      In this paper, we present a new method to mitigate the effect of the charge collected by trigate FinFET devices after an ionizing particle impact. The method is based on the creation of an internal structure that generates ...
    • Adaptive fault-tolerant architecture for unreliable device technologies 

      Aymerich, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (CRC Press, Taylor and Francis Group, 2013-06-03)
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      Nanoelectronic Device Applications Handbook gives a comprehensive snapshot of the state of the art in nanodevices for nanoelectronics applications. Combining breadth and depth, the book includes 68 chapters on topics that ...
    • Adaptive fault-tolerant architecture for unreliable device technologies 

      Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
      Conference report
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      This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We define an adaptive averaging ...
    • Adaptive fault-tolerant architecture for unreliable technologies with heterogeneous variability 

      Aymerich Capdevila, Nivard; Cotofana, Sorin; Rubio Sola, Jose Antonio (2012-07)
      Article
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      This paper introduces an efficient adaptive redundant architecture, which makes use of the averaging cell (AVG) principle in order to improve the reliability of nanoscale circuits and systems. We propose an adaptive structure ...
    • Adaptive proactive reconfiguration: a technique for process variability and aging aware SRAM cache design 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (2014)
      Article
      Open Access
      Nanoscale circuits are subject to a wide range of new limiting phenomena making essential to investigate new design strategies at the circuit and architecture level to improve its performance and reliability. Proactive ...
    • Advanced failure detection techniques in deep submicron CMOS integrated circuits 

      Rubio Sola, Jose Antonio; Altet Sanahujes, Josep; Mateo Peña, Diego (Pergamon Press, 2009)
      Conference report
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      The test of present integrated circuits exhibits many confining aspects, among them the adequate selection of the observable variables, the use of combined testing approaches, an each time more restricted controllability ...
    • An academic RISC-V silicon implementation based on open-source components 

      Abella Ferrer, Jaume; Bulla, Calvin; Cabo Pitarch, Guillem; Cazorla Almeida, Francisco Javier; Cristal Kestelman, Adrián; Doblas Font, Max; Figueras Bagué, Roger; González Trejo, Alberto; Hernández Luz, Carles; Hernández Calderón, César Alejandro; Jiménez Arador, Víctor; Kosmidis, Leonidas; Kostalabros, Ioannis-Vatistas; Langarita Benítez, Rubén; Leyva Santes, Neiel; López Paradís, Guillem; Marimon Illana, Joan; Martínez Martínez, Ricardo; Mendoza Escobar, Jonnatan; Moll Echeto, Francisco de Borja; Moreto Planas, Miquel; Pavón Rivera, Julián; Ramírez Lazo, Cristóbal; Ramírez Salinas, Marco Antonio; Rojas Morales, Carlos; Rubio Sola, Jose Antonio; Ruiz, Abraham Josafat; Sonmez, Nehir; Soria Pardos, Víctor; Teres Teres, Lluis; Unsal, Osman Sabri; Valero Cortés, Mateo; Vargas Valdivieso, Iván; Villa Vargas, Luis Alfonso (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ...
    • An on-line test strategy and analysis for a 1T1R crossbar memory 

      Escudero, Manel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Vourkas, Ioannis (Institute of Electrical and Electronics Engineers (IEEE), 2017)
      Conference report
      Open Access
      Memristors are emerging devices known by their nonvolability, compatibility with CMOS processes and high density in circuits density in circuits mostly owing to the crossbar nanoarchitecture. One of their most notable ...
    • Analysis and modelling of parasitic substrate coupling in CMOS circuits 

      Aragonès Cervera, Xavier; Moll Echeto, Francisco de Borja; Roca Adrover, Miquel; Rubio Sola, Jose Antonio (1995-10)
      Article
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      Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling ...