Now showing items 1-6 of 6

  • A FM-index transformation to enable large k-steps 

    Langarita, Rubén; Armejach Sanosa, Adrià; Moreto Planas, Miquel (Barcelona Supercomputing Center, 2019-05-07)
    Conference report
    Open Access
  • Exploration of architectural parameters for future HPC systems 

    Gómez, Constantino; Martínez, Francesc; Armejach Sanosa, Adrià; Casas, Marc; Mantovani, Filippo; Moreto Planas, Miquel (Barcelona Supercomputing Center, 2019-05-07)
    Conference report
    Open Access
  • Parallel-Architecture Simulator Development Using Hardware Transactional Memory 

    Armejach Sanosa, Adrià (Universitat Politècnica de Catalunya, 2009-09-23)
    Master thesis
    Open Access
    To address the need for a simpler parallel programming model, Transactional Memory (TM) has been developed and promises good parallel performance with easy-to-write parallel code. Unlike lock-based approaches, with TM, ...
  • Stencil codes on a vector length agnostic architecture 

    Armejach Sanosa, Adrià; Caminal Pallarés, Helena; Cebrián González, Juan Manuel; González-Alberquilla, Rekai; Adeniyi-Jones, Chris; Valero Cortés, Mateo; Casas, Marc; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2018)
    Conference report
    Open Access
    Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ...
  • Techniques to improve concurrency in hardware transactional memory 

    Armejach Sanosa, Adrià (Universitat Politècnica de Catalunya, 2014-06-13)
    Doctoral thesis
    Open Access
    Transactional Memory (TM) aims to make shared memory parallel programming easier by abstracting away the complexity of managing shared data. The programmer defines sections of code, called transactions, which the TM system ...
  • Using Arm’s scalable vector extension on stencil codes 

    Armejach Sanosa, Adrià; Caminal Pallarés, Helena; Cebrián González, Juan Manuel; Langarita, Rubén; González-Alberquilla, Rekai; Adeniyi-Jones, Chris; Valero Cortés, Mateo; Casas Guix, Marc; Moreto Planas, Miquel (2019-04-08)
    Article
    Restricted access - publisher's policy
    Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ...