Now showing items 1-7 of 7

  • Architectural exploration of large-scale hierarchical chip multiprocessors 

    Nikitin, Nikita; San Pedro Martín, Javier de; Cortadella, Jordi (2013)
    Article
    Restricted access - publisher's policy
    The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ...
  • Automatic synthesis and optimization of chip multiprocessors 

    Nikitin, Nikita (Universitat Politècnica de Catalunya, 2013-04-05)
    Doctoral thesis
    Open Access
    The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental ...
  • Physical-aware link allocation and route assignment for chip multiprocessing 

    Nikitin, Nikita; Chatterjee, Satrajit; Cortadella, Jordi; Kishinevsky, Michael; Ogras, Umit (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Open Access
    The architecture definition, design, and validation of the interconnect networks is a key step in the design of modern on-chip systems. This paper proposes a mathematical formulation of the problem of simultaneously defining ...
  • Physical-aware system-level design for tiled hierarchical chip multiprocessors 

    Cortadella, Jordi; San Pedro Martín, Javier de; Nikitin, Nikita; Petit Silvestre, Jordi (ACM Press. Association for Computing Machinery, 2013)
    Conference report
    Open Access
    Tiled hierarchical architectures for Chip Multiprocessors (CMPs) represent a rapid way of building scalable and power-e fficient many-core computing systems. At the early stages of the design of a CMP, physical parameters ...
  • Physical planning for the architectural exploration of large-scale chip multiprocessors 

    San Pedro Martín, Javier de; Nikitin, Nikita; Cortadella, Jordi; Petit Silvestre, Jordi (2013)
    Conference lecture
    Restricted access - publisher's policy
    This paper presents an integrated flow for architectural exploration and physical planning of large-scale hierarchical tiled CMPs. Classical floorplanning and wire planning techniques have been adapted to incorporate layout ...
  • Static task mapping for tiled chip multiprocessors with multiple voltage islands 

    Nikitin, Nikita; Cortadella, Jordi (Springer Verlag, 2012)
    Conference report
    Restricted access - publisher's policy
    The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping ...
  • Static task mapping for tiled chip multiprocessors with multiple voltage islands 

    Nikitin, Nikita; Cortadella, Jordi (2011)
    External research report
    Open Access
    The complexity of large Chip Multiprocessors (CMP) makes design reuse a practical approach to reduce the manufacturing and design cost of high-performance systems. This paper proposes techniques for static task mapping ...