Now showing items 1-20 of 32

  • A case for resource-conscious out-of-order processors 

    Cristal Kestelman, Adrián; Martínez, José F; Llosa Espuny, José Francisco; Valero Cortés, Mateo (2003-12)
    Article
    Open Access
    Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files ...
  • A low cost split-issue technique to improve performance of SMT clustered VLIW processors 

    Gupta, Manoj; Sánchez Carracedo, Fermín; Llosa Espuny, José Francisco (2010)
    Conference report
    Open Access
    Abstract—Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreading (SMT) is a popular technique for ...
  • An efficient solver for Cache Miss Equations 

    Bermudo, Nerina; Vera Rivera, Francisco Javier; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Conference report
    Open Access
    Cache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ...
  • Aprendizaje activo basado en problemas 

    Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Llosa Espuny, José Francisco; Sánchez Carracedo, Fermín (Universitat Jaume I. Escola Superior de Tecnologia i Ciències Experimentals, 2013-07-10)
    Conference report
    Open Access
    Durante años, los autores del presente trabajo hemos practicado diversos métodos para fomentar el aprendizaje activo de los estudiantes a partir de la resolución de problemas, tanto en clase como fuera de ella. Los ...
  • Aprenentatge actiu basat en problemes 

    Llosa Espuny, José Francisco; Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Sánchez Carracedo, Fermín (Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2014-04-24)
    Conference report
    Open Access
    Durant anys, els autors del present treball hem practicat diversos mètodes per fomentar l'aprenentatge actiu dels estudiants a partir de la resolució de problemes, tant a la classe com fora. Els últims quatre cursos hem ...
  • Cost-conscious strategies to increase performance of numerical programs on agressive VLIW architectures 

    López Álvarez, David; Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (2001-10)
    Article
    Open Access
    Loops are the main time-consuming part of numerical applications. The performance of the loops is limited either by the resources offered by the architecture or by recurrences in the computation. To execute more operations ...
  • El impacto de eliminar el examen final 

    Llosa Espuny, José Francisco; Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Sánchez Carracedo, Fermín (2016-09)
    Article
    Open Access
    Desde hace algún tiempo se publican en JENUI artículos donde se argumenta sobre la conveniencia de eliminar el examen final como forma de fomentar el trabajo del estudiante durante todo el curso. Convencidos de lo apropiado ...
  • Evaluación formativa con feedback rápido usando mandos interactivos 

    Álvarez Martínez, Carlos; Llosa Espuny, José Francisco (Universidade de Santiago de Compostela. Escola Técnica Superior d'Enxeñaría, 2010-07-07)
    Conference lecture
    Open Access
    Numerosos estudios han demostrado que el uso del feedback como herramienta docente resulta beneficioso para el aprendizaje. Para que este feedback sea útil debe ser rápido, es decir, llegar al alumno poco después de ...
  • Heuristics for register-constrained software pipelining 

    Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1996)
    Conference report
    Open Access
    Software Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal ...
  • Hierarchical clustered register file organization for VLIW processors 

    Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (IEEE Computer Society, 2003)
    Conference report
    Open Access
    Technology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned ...
  • Hybrid multithreading for VLIW processors 

    Gupta, Manoj; Sánchez Carracedo, Fermín; Llosa Espuny, José Francisco (2009-10)
    Conference report
    Open Access
    Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor ...
  • Hypernode reduction modulo scheduling 

    Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Conference report
    Open Access
    Software pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution ...
  • El Impacto de eliminar el examen final 

    Llosa Espuny, José Francisco; Álvarez Martínez, Carlos; Fernández Jiménez, Agustín; Sánchez Carracedo, Fermín (Universidad de Almería, 2016-07-06)
    Conference lecture
    Open Access
    Desde hace algún tiempo se publican en JENUI artículos donde se argumenta sobre la conveniencia de eliminar el examen final como forma de fomentar el trabajo del estudiante durante todo el curso. Convencidos de lo apropiado ...
  • Impact on performance of fused multiply-add units in aggressive VLIW architectures 

    López Álvarez, David; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the resources offered by the architecture. ...
  • Incorporació de sistemes de resposta interactiva a la docència presencial 

    Sánchez Carracedo, Fermín; Fonseca, Pau; Delgado Mercè, Jaime; Llorente Viejo, Silvia; Cerda, Llorenç; Llosa Espuny, José Francisco; Álvarez, Carlos; Sesé Castel, Gemma; Bravo Amella, Hector; Moralhelche Piulachs, Jordi (Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2010-02-11)
    Conference lecture / Conference report
    Open Access
    Aquest projecte, de Suport a la Docència, consisteix en la incorporació d’uns comandaments amb botons del 0 al 9 a les classes per tal de donar suport als professors a les seves classes i, d’aquesta manera, avaluar els ...
  • Lifetime-sensitive modulo scheduling in a production environment 

    Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; González Colás, Antonio María; Valero Cortés, Mateo; Eckhardt, Jason (2001-03)
    Article
    Open Access
    This paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS). It generates schedules that are near optimal in terms of initiation interval, register requirements, and stage count. ...
  • Mirs: modulo scheduling with integrated register spilling 

    Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (2003-01)
    Article
    Restricted access - publisher's policy
    The overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ...
  • Modulo scheduling with integrated register spilling for clustered VLIW architectures 

    Zalamea León, Francisco Javier; Llosa Espuny, José Francisco; Ayguadé Parra, Eduard; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    Clustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers ...
  • Modulo scheduling with reduced register pressure 

    Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard; González Colás, Antonio María (1998-06)
    Article
    Open Access
    Software pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for ...
  • Near-optimal loop tiling by means of cache miss equations and genetic algorithms 

    Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...