Now showing items 1-13 of 13

    • A confidence assessment of WCET estimates for software time randomized caches 

      Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Obtaining Worst-Case Execution Time (WCET) estimates is a required step in real-time embedded systems during software verification. Measurement-Based Probabilistic Timing Analysis (MBPTA) aims at obtaining WCET estimates ...
    • Behavior characterization of the shared last-level cache in a chip multiprocessor 

      Benedicte Illescas, Pedro (Universitat Politècnica de Catalunya, 2014-06-27)
      Master thesis (pre-Bologna period)
      Open Access
      [CATALÀ] Aquest projecte consisteix a analitzar diferents aspectes de la jerarquia de memòria i entendre la seva influència al rendiment del sistema. Els aspectes que s'analitzaran són els algorismes de reemplaçament, els ...
    • Design and integration of hierarchical-placement multi-level caches for real-Time systems 

      Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2018)
      Conference report
      Restricted access - publisher's policy
      Enabling timing analysis in the presence of caches has been pursued by the real-Time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst-case execution time (WCET). However, ...
    • HWP: hardware support to reconcile cache energy, complexity, performance and WCET estimates in multicore real-time systems 

      Benedicte Illescas, Pedro; Hernandez, C.; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2018)
      Conference report
      Open Access
      High-performance processors have deployed multilevel cache (MLC) systems for decades. In the embedded real-time market, the use of MLC is also on the rise, with processors for future systems in space, railway, avionics and ...
    • Improving time-randomized cache design 

      Benedicte Illescas, Pedro; Hernández Gañán, Carlos; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Barcelona Supercomputing Center, 2018-04-24)
      Conference report
      Open Access
      Enabling timing analysis for caches has been pursued by the critical real-time embedded systems (CRTES) community for years due to their potential to reduce worstcase execution times (WCET). Measurement-based protabilistic ...
    • Locality-aware cache random replacement policies 

      Benedicte Illescas, Pedro; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Elsevier, 2019-02)
      Article
      Restricted access - publisher's policy
      Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ...
    • Locality-aware cache random replacement policies 

      Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (2019-02-01)
      Article
      Restricted access - publisher's policy
      Measurement-Based Probabilistic Timing Analysis (MBPTA) facilitates the analysis of complex software running on hardware comprising high-performance features. MBPTA also aims at preventing additional analysis costs for ...
    • Modeling contention interference in crossbar-based systems via Sequence-Aware Pairing (SeAP) 

      Giesen, Jeremy; Benedicte Illescas, Pedro; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      The Infineon AURIX TriCore family of microcontrollers has consolidated as the reference multicore computing platform for safety-critical systems in the automotive domain. As a distinctive trait, AURIX microcontrollers are ...
    • Modelling the confidence of timing analysis for time randomised caches 

      Benedicte Illescas, Pedro; Kosmidis, Leonidas; Quiñones, Eduardo; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2016)
      Conference report
      Open Access
      Timing is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ...
    • On the analysis of the timing behaviour of time randomised caches 

      Benedicte Illescas, Pedro (Universitat Politècnica de Catalunya, 2016-07-07)
      Master thesis
      Open Access
      Time Randomised caches (TRc), which can be implemented at hardware level or with software means on conventional deterministic cache designs, have been proposed for real-time systems as key enablers for Probabilistic ...
    • Performance analysis and optimization of automotive GPUs 

      Mazzocchetti, Fabio; Benedicte Illescas, Pedro; Tabani, Hamid; Kosmidis, Leonidas; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Open Access
      Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) have drastically increased the performance demands of automotive systems. Suitable highperformance platforms building upon Graphic Processing Units ...
    • RPR: a random replacement policy with limited pathological replacements 

      Benedicte Illescas, Pedro; Hernández Luz, Carles; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018)
      Conference report
      Restricted access - publisher's policy
      Measurement-Based Probabilistic Timing Analysis (MBPTA) has consolidated as a technique to estimate probabilistic Worst-Case Execution Times (WCET) for critical software running on processors with high-performance hardware ...
    • Towards limiting the impact of timing anomalies in complex real-time processors 

      Benedicte Illescas, Pedro; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier; Hernández Luz, Carles (2019)
      Conference report
      Restricted access - publisher's policy
      Timing verification of embedded critical real-time systems is hindered by complex designs. Timing anomalies, deeply analyzed in static timing analysis, require specific solutions to bound their impact. For the first time, ...