Browsing by Author "López Paradís, Guillem"
Now showing items 1-12 of 12
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An academic RISC-V silicon implementation based on open-source components
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessThe design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V ... -
Characterization of a coherent hardware accelerator framework for SoCs
(Springer, 2023)
Conference report
Restricted access - publisher's policyAccelerators rich architectures have become the standard in today’s SoCs. After Moore’s law diminish, it is common to only dedicate a fraction of the area of the SoC to traditional cores and leave the rest of space for ... -
DVINO: A RISC-V vector processor implemented in 65nm technology
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference lecture
Open AccessThis paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM ... -
Evaluating the impact of future memory technologies in the design of multicore processors
(Universitat Politècnica de Catalunya, 2017-01)
Bachelor thesis
Open Access"It’s the Memory, Stupid!" In 1996, Richard Sites, one of the fathers of Computer Architecture and lead designer of the DEC alpha, wrote a paper [36] with the title above. In that paper he realized that the only important ... -
Fast behavioural RTL simulation of 10B transistor SoC designs with Metro-Mpi
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference report
Open AccessChips with tens of billions of transistors have become today's norm. These designs are straining our electronic design automation tools throughout the design process, requiring ever more computational resources. In many ... -
gem5 + rtl: A framework to enable RTL models inside a full-system simulator
(Association for Computing Machinery (ACM), 2021)
Conference report
Open AccessIn recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system ... -
GenArchBench: A genomics benchmark suite for arm HPC processors
(Elsevier, 2024-08)
Article
Open AccessArm usage has substantially grown in the High-Performance Computing (HPC) community. Japanese supercomputer Fugaku, powered by Arm-based A64FX processors, held the top position on the Top500 list between June 2020 and June ... -
Mont-Blanc 2020: Towards scalable and power efficient European HPC processors
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessThe Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European ... -
OpenPiton optimizations towards high performance manycores
(Association for Computing Machinery (ACM), 2023)
Conference report
Open AccessIn recent years, numerous multicore RISC-V platforms have emerged. Within the RISC-V ecosystem, Networks-on-Chip (NoCs) such as OpenPiton are employed in designs that aim to scale to a large number of cores. This paper ... -
Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Conference report
Open AccessThe RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing ... -
Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference lecture
Open AccessThis paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ... -
Towards the simulation and emulation of large-scale hardware designs
(Universitat Politècnica de Catalunya, 2020-10-29)
Master thesis
Open AccessThe heritage of Moore's law has converged in a heterogeneous processor with a many-core and different application- or domain-specific accelerators. Having also finished the benefits of Dennard scaling, we have ended up in ...
