Browsing by Author "Espasa Sans, Roger"
Now showing items 1-18 of 18
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A case for merging the ILP and DLP paradigms
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved ... -
A SIMD-efficiant 14 instruction shader program for high-throughput microtriangle rasterization
(Springer Verlag, 2010)
Conference report
Restricted access - publisher's policyThis paper shows that breaking the barrier of 1 triangle/clock rasterization rate for microtriangles in modern GPU architectures in an efficient way is possible. The fixed throughput of the special purpose culling and ... -
An evaluation of different DLP alternatives for the embedded media domain
(1999)
Conference report
Open AccessThe importance of media processing has produced a revolution in the design of embedded processors. In order to face the high computational and technological demands of near future media applications, new embedded processors ... -
Command vector memory systems: high performance at low cost
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe focus of this paper is on designing both a low cost and high performance, high bandwidth vector memory system that takes advantage of modern commodity SDRAM memory chips. To successfully extract the full bandwidth from ... -
Decoupled vector architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Conference report
Open AccessThe purpose of this paper is to show that using decoupling techniques in a vector processor, the performance of vector programs can be greatly improved. Using a trace driven approach, we simulate a selection of the Perfect ... -
DLP+TLP processors for the next generation of media workloads
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Conference report
Open AccessFuture media workloads will require about two levels of magnitude the performance achieved by current general purpose processors. High uni-threaded performance will be needed to accomplish real-time constraints together ... -
Effective usage of vector registers in advanced vector architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThis paper presents data confirming the fact that traditional vector architectures can not reduce their vector register length without suffering a severe performance penalty. However, we will show that by combining the ... -
Effective usage of vector registers in decoupled vector architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1998)
Conference report
Open AccessThe paper presents a study of the impact of reducing the vector register size in a decoupled vector architecture. In traditional in-order vector architectures long vector registers have typically been the norm. The authors ... -
Exploiting a new level of DLP in multimedia applications
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessThis paper proposes and evaluates MOM: a novel ISA paradigm targeted at multimedia applications. By fusing conventional vector ISA approaches together with more recent SIMD-like (Single Instruction Multiple Data) ISAs (such ... -
Exploiting instruction-and data-level parallelism
(1997-09)
Article
Open AccessSimultaneous multithreaded vector architectures combine the best of data-level and instruction-level parallelism and perform better than either approach could separately. Our design achieves performance equivalent to ... -
MOM: a matrix SIMD instruction set architecture for multimedia applications
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Conference report
Open AccessMOM is a novel matrix-oriented ISA paradigm for multimedia applications, based on fusing conventional vector ISAs with SIMD ISAs such as MMX. This paper justifies why MOM is a suitable alternative for the multimedia domain ... -
Multithreaded vector architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessThe purpose of this paper is to show that multi-threading techniques can be applied to a vector processor to greatly increase processor throughput and maximize resource utilization. Using a trace driven approach, we simulate ... -
On the efficiency of reductions in µ-SIMD media extensions
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Conference report
Open AccessMany important multimedia applications contain a significant fraction of reduction operations. Although, in general, multimedia applications are characterized for having high amounts of Data Level Parallelism, reductions ... -
Out-of-order vector architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessRegister renaming and out-of-order instruction issue are now commonly used in superscalar processors. These techniques can also be used to significant advantage in vector processors, as this paper shows. Performance is ... -
Processor Design
(Universitat Politècnica de Catalunya, 2017)
Lecture notes
Open Access -
Quantitative analysis of vector code
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Conference report
Open AccessIn this paper we present the results of a detailed simulation study of the execution of vector programs on a single processor of a Convex C3480 machine, using a subset of the Perfect Club benchmarks. We are interested in ... -
Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
Conference report
Open AccessShows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that ... -
Three-dimensional memory vectorization for high bandwidth media memory systems
(Institute of Electrical and Electronics Engineers (IEEE), 2002)
Conference report
Open AccessVector processors have good performance, cost and adaptability when targeting multimedia applications. However, for a significant number of media programs, conventional memory configurations fail to deliver enough memory ...
