Browsing by Author "Vavouliotis, Georgios"

Now showing items 1-7 of 7

    • A two level neural approach combining off-chip prediction with adaptive prefetch filtering 

      Jamet, Alexandre Valentin; Vavouliotis, Georgios; Jiménez, Daniel A.; Álvarez Martí, Lluc; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      To alleviate the performance and energy overheads of contemporary applications with large data footprints, we propose the Two Level Perceptron (TLP) predictor, a neural mechanism that effectively combines predicting whether ...

    • Advanced hardware prefetching in virtual memory systems 

      Vavouliotis, Georgios (Universitat Politècnica de Catalunya, 2023-09-12)
      Doctoral thesis
      Open Access
      (English) Despite groundbreaking technological innovations, the disparity between processor and memory speeds (known as Memory Wall) is still a major performance obstacle for modern systems. Hardware prefetching is a ...

    • Exploiting page table locality for Agile TLB Prefetching 

      Vavouliotis, Georgios; Alvarez Martí, Lluc; Karakostas, Vasileios; Nikas, Konstantinos; Koziris, Nectarios; Jiménez, Daniel A.; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      Frequent Translation Lookaside Buffer (TLB) misses incur high performance and energy costs due to page walks required for fetching the corresponding address translations. Prefetching page table entries (PTEs) ahead of ...

    • Morrigan: A composite instruction TLB prefetcher 

      Vavouliotis, Georgios; Alvarez Martí, Lluc; Grot, Boris; Jiménez, Daniel A.; Casas, Marc (Association for Computing Machinery (ACM), 2021)
      Conference report
      Open Access
      The effort to reduce address translation overheads has typically targeted data accesses since they constitute the overwhelming portion of the second-level TLB (STLB) misses in desktop and HPC applications. The address ...

    • Page size aware cache prefetching 

      Vavouliotis, Georgios; Chacon, Gino; Álvarez Martí, Lluc; Gratz, Paul V.; Jiménez, Daniel A.; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2022)
      Conference report
      Open Access
      The increase in working set sizes of contemporary applications outpaces the growth in cache sizes, resulting in frequent main memory accesses that deteriorate system per- formance due to the disparity between processor and ...

    • Practically tackling memory bottlenecks of graph-processing workloads 

      Jamet, Alexandre Valentin; Vavouliotis, Georgios; Jiménez, Daniel A.; Álvarez Martí, Lluc; Casas, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2024)
      Conference report
      Open Access
      Graph-processing workloads have become widespread due to their relevance on a wide range of application domains such as network analysis, path- planning, bioinformatics, and machine learning. Graph-processing workloads ...

    • Pushing the envelope on free TLB prefetching 

      Vavouliotis, Georgios; Álvarez Martí, Lluc; Casas, Marc (Barcelona Supercomputing Center, 2021-05)
      Conference report
      Open Access
      Frequent Translation Lookaside Buffer (TLB) misses pose significant performance and energy overheads due to page walks required for fetching the translations. The address translation performance bottleneck is further ...