Now showing items 1-20 of 32

    • A Divide-and-Conquer Approach for Cell Routing using Litho-friendly Layouts 

      Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2013-06-17)
      Master thesis (pre-Bologna period)
      Restricted access - confidentiality agreement
    • A Simulation framework for hierarchical Network-on-Chip systems 

      San Pedro Martín, Javier de (Universitat Politècnica de Catalunya, 2012-06-22)
      Master thesis
      Open Access
      Today, even the simplest laptop processor has at least four cores and a graphics card containing tens of cores. It is not hard to find more performance- oriented processors with hundreds of cores, and it is expected to ...
    • Algorithmic and architectural techniques for the design of low-energy resilient applications 

      Moreno Vega, Alberto (Universitat Politècnica de Catalunya, 2013-06)
      Master thesis (pre-Bologna period)
      Restricted access - confidentiality agreement
    • Algorithmic techniques for physical design : macro placement and under-the-cell routing 

      Vidal Obiols, Alexandre (Universitat Politècnica de Catalunya, 2020-01-24)
      Doctoral thesis
      Open Access
      With the increase of chip component density and new manufacturability constraints imposed by modern technology nodes, the role of algorithms for electronic design automation is key to the successful implementation of ...
    • Algorithms and methodologies for interconnect reliability analysis of integrated circuits 

      Jain, Palkesh (Universitat Politècnica de Catalunya, 2017-05-05)
      Doctoral thesis
      Open Access
      The phenomenal progress of computing devices has been largely made possible by the sustained efforts of semiconductor industry in innovating techniques for extremely large-scale integration. Indeed, gigantically integrated ...
    • An environment for the automatic verification of digital circuits 

      San Pedro Martín, Javier de (Universitat Politècnica de Catalunya, 2011-05-17)
      Master thesis (pre-Bologna period)
      Open Access
      English: The aim of this project is to implement a system for the automatic verification of digital circuits written in a high-level hardware description language (Verilog), to be potentially used to assist a electronic ...
    • Architectural Layout Design with Spectral Methods 

      Folguera Profitós, Júlia (Universitat Politècnica de Catalunya, 2020-10)
      Master thesis
      Open Access
      The design of a floor plan is an important phase of the design of an apartment, although it is very complex due to the quantity of variables involved. The mathematical version of this problem is the architectural layout ...
    • Automatic synthesis and optimization of chip multiprocessors 

      Nikitin, Nikita (Universitat Politècnica de Catalunya, 2013-04-05)
      Doctoral thesis
      Open Access
      The microprocessor technology has experienced an enormous growth during the last decades. Rapid downscale of the CMOS technology has led to higher operating frequencies and performance densities, facing the fundamental ...
    • Clustering for the optimisation of asynchronous controllers 

      Casanova Bachs, Jonàs (Universitat Politècnica de Catalunya, 2008-06-25)
      Master thesis
      Open Access
    • Design of an environment for solving pseudo-boolean optimization problems 

      Benedí, Marc (Universitat Politècnica de Catalunya, 2018-06-26)
      Bachelor thesis
      Open Access
      This dissertation addresses several approaches with the common goal of reducing the time required to solve Pseudo-Boolean minimisation problems. A C++ library has been developed which allows representing Pseudo-Boolean ...
    • Disseny i implementació d'un processador en un llenguatge de descripció de Hardware 

      Miralpeix Anglerill, Marta (Universitat Politècnica de Catalunya, 2011-03-01)
      Master thesis (pre-Bologna period)
      Open Access
      Aquest propòsit és el fil conductor del projecte, del qual es deriven quatre objectius més concrets: Disseny del processador CAL16, sempre complint les característiques de modularitat i extensibilitat, fet que permetrà ...
    • Elastic Esterel 

      Galcerán Oms, Marc (Universitat Politècnica de Catalunya, 2007-06-25)
      Master thesis
      Open Access
      The aim of this master's thesis is to elasticize Esterel. Esterel is an imperative hardware description language (HDL) used to describe reactive systems, and oriented to specify control systems. It belongs to the family ...
    • Enhancing large format printer reliability using machine learning 

      Badia Sampera, Arnau (Universitat Politècnica de Catalunya, 2018-07-04)
      Bachelor thesis
      Restricted access - confidentiality agreement
      Covenantee:   Hewlett-Packard Company
    • Explorando factores de riesgo de insuficiencia cardíaca a través del aprendizaje automático 

      Pérez Soria, Beatriz (Universitat Politècnica de Catalunya, 2019-02)
      Bachelor thesis
      Open Access
      Acute myocardial infarction is one of the main causes of mortality in developed countries. There are many risk factors that can trigger a heart attack that have to do with our lifestyle today. One of the most complicated ...
    • From high-level languages to dataflow circuits 

      Marset Alsina, Joaquim (Universitat Politècnica de Catalunya, 2019-07)
      Bachelor thesis
      Open Access
      La manera tradicional de computar alguna cosa és creant software que es pot executar en la unitat de processament central (CPU) d'un processador. El problema és que una CPU no té la capacitat de còmput suficient per executar ...
    • Heart Failure Factors: a database approach 

      Gállego Olsina, Gerard Ion (Universitat Politècnica de Catalunya, 2019-03)
      Bachelor thesis
      Open Access
      This project aims to find relationships between psychological stress factors and heart attacks that took place in Catalunya between 2010 and 2016. We have measured these factors through the news that were published in La ...
    • Library-free technology mapping for VLSI circuits with regular layouts 

      Alvarez Ruiz, Alex (Universitat Politècnica de Catalunya, 2014-07)
      Master thesis
      Open Access
      Technology mapping is the task to transform a technology independent logic network into a mapped network using gates from a library, optimizing some objective function such total area, delay or power consumption. As stated, ...
    • Logic decomposition and adaptive clocking for the optimization of digital circuits 

      Machado, Lucas (Universitat Politècnica de Catalunya, 2019-02-21)
      Doctoral thesis
      Open Access
      Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous ...
    • Loop pipelining with resource and timing constraints 

      Sánchez Carracedo, Fermín (Universitat Politècnica de Catalunya, 1996-01-12)
      Doctoral thesis
      Open Access
      Developing efficient programs for many of the current parallel computers is not easy due to the architectural complexity of those machines. The wide variety of machine organizations often makes it more difficult to port ...
    • Machine learning techniques for resource prediction in nanoelectronic circuit design 

      Ricart Geli, Narcís (Universitat Politècnica de Catalunya, 2017-07-03)
      Master thesis
      Open Access
      This master’s thesis is about the use of machine learning techniques in the field of nanoelectronic circuit design. It has been developed in collaboration with eSilicon Corporation, which is a company specialized in ...