Now showing items 1-20 of 169

  • A boolean rule-based approach for manufacturability-aware cell routing 

    Cortadella, Jordi; Petit Silvestre, Jordi; Gómez Fernández, Sergio; Moll Echeto, Francisco de Borja (2014-03-01)
    Article
    Open Access
    An approach for cell routing using gridded design rules is proposed. It is technology-independent and parameterizable for different fabrics and design rules, including support for multiple-patterning lithography. The core ...
  • A case study for the verification of complex timed circuits: IPCMOS 

    Peña Basurto, Marco Antonio; Cortadella, Jordi; Pastor Llorens, Enric; Smirnov, Alexandre (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ...
  • A compositional method for the synthesis of asynchronous communication mechanisms 

    Costa Gorgônio, Kyller; Cortadella, Jordi; Xia, Fei (Springer, 2007-06-30)
    Part of book or chapter of book
    Open Access
    Asynchronous data communication mechanisms (ACMs) have been extensively studied as data connectors between independently timed concurrent processes. In previous work, an automatic ACM synthesis method based on the generation ...
  • Adaptive clock with useful jitter 

    Cortadella, Jordi; Lavagno, Luciano; López Muñoz, Pedro; Lupon Navazo, Marc; Moreno Vega, Alberto; Roca Pérez, Antoni; Sapatnekar, Sachin S. (2015-05-19)
    External research report
    Open Access
    The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...
  • A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects 

    Jain, Palkesh; Cortadella, Jordi; Sapatnekar, Sachin S. (2016-06-01)
    Article
    Open Access
    A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and ...
  • A general model for performance optimization of sequential systems 

    Bufistov, Dmitry; Cortadella, Jordi; Kishinevsky, Michael; Sapatnekar, Sachin S. (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    Retiming, c-slow retiming and recycling are different transformations for the performance optimization of sequential circuits. For retiming and c-slow retiming, different models that provide exact solutions have already ...
  • A hierarchical approach for generating regular floorplans 

    San Pedro Martín, Javier de; Cortadella, Jordi; Roca Pérez, Antoni (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    The complexity of the VLSI physical design flow grows dramatically as the level of integration increases. An effective way to manage this increasing complexity is through the use of regular designs which contain more ...
  • A hierarchical mathematical model for automatic pipelining and allocation using elastic systems 

    Cortadella, Jordi; Petit Silvestre, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2018)
    Conference report
    Open Access
    The advent of FPGA-based accelerators has encouraged the use of high-level synthesis (HLS) for rapid prototyping and design space exploration. In this context, design optimization at behavioral level becomes a critical ...
  • A mathematical formulation of the loop pipelining problem 

    Cortadella, Jordi; Badia Sala, Rosa Maria; Sánchez Carracedo, Fermín (Universitat Politècnica de Catalunya (UPC), 1996)
    Conference report
    Open Access
    This paper presents a mathematical model for the loop pipelining problem that considers several parameters for optimization and supports any combination of resource and timing constraints. The unrolling degree of the loop ...
  • A multi-radix approach to asynchronous division 

    Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Conference report
    Open Access
    The speed of high-radix digit-recurrence dividers is mainly determined by the hardware complexity of the quotient-digit selection function. In this paper we present a scheme that combines the area efficiency of bundled ...
  • An asynchronous architecture model for behavioral synthesis 

    Cortadella, Jordi; Badia Sala, Rosa Maria (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Conference report
    Open Access
    An asynchronous architecture model for behavioral synthesis is presented. The basis of the model lies in a distributed control structure consisting of multiple communicating processes. Data processing is performed by ...
  • An efficient unique state coding algorithm for signal transition graphs 

    Pastor Llorens, Enric; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Conference report
    Open Access
    Current algorithms to force the complete state coding (CSC) property for signal transition graphs work on the state graph and, therefore require exponential time and space. Polynomial algorithms have been only proposed for ...
  • A new look at the conditions for the synthesis of speed-independent circuits 

    Pastor Llorens, Enric; Cortadella, Jordi; Roig Mansilla, Oriol (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Conference report
    Open Access
    This paper presents a set of sufficient conditions for the gate-level synthesis of speed-independent circuits when constrained to a given class of gate library. Existing synthesis methodologies are restricted to architectures ...
  • A radix-16 SRT division unit with speculation of the quotient digits 

    Gianluca, Cornetta; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    The speed of a divider based on a digit-recurrence algorithm depends mainly on the latency of the quotient digit generation function. In this paper we present an analytical approach that extends the theory developed for ...
  • Architectural exploration of large-scale hierarchical chip multiprocessors 

    Nikitin, Nikita; San Pedro Martín, Javier de; Cortadella, Jordi (2013)
    Article
    Restricted access - publisher's policy
    The continuous scaling of nanoelectronics is increasing the complexity of chip multiprocessors (CMPs) and exacerbating the memory wall problem. As CMPs become more complex, the memory subsystem is organized into more ...
  • Area-optimal transistor folding for 1-D gridded cell design 

    Cortadella, Jordi (2013-11)
    Article
    Open Access
    The 1-D design style with gridded design rules is gaining ground for addressing the printability issues in subwavelength photolithography. One of the synthesis problems in cell generation is transistor folding, which ...
  • A recursive paradigm to solve boolean relations 

    Baneres, David; Cortadella, Jordi; Kishinevsky, Michael (Institute of Electrical and Electronics Engineers (IEEE), 2009-04)
    Article
    Open Access
    A Boolean relation can specify some types of flexibility of a combinational circuit that cannot be expressed with don't cares. Several problems in logic synthesis, such as Boolean decomposition or multilevel minimization, ...
  • A region-based algorithm for discovering Petri nets from event logs 

    Carmona Vargas, Josep; Cortadella, Jordi; Kishinevsky, Michael (Springer, 2008)
    Conference report
    Open Access
    The paper presents a new method for the synthesis of Petri nets from event logs in the area of Process Mining. The method derives a bounded Petri net that over-approximates the behavior of an event log. The most important ...
  • A region-based theory for state assignment in speed-independent circuits 

    Cortadella, Jordi; Kishinevsky, Michael; Kondratyev, Alex; Lavagno, Luciano; Yakovlev, Alex (1997-08)
    Article
    Open Access
    State assignment problems still need satisfactory solutions to make asynchronous circuit synthesis more practical. A well-known example of such a problem is that of complete state coding (CSC), which happens when a pair ...
  • A Relational view of subgraph isomorphism 

    Cortadella, Jordi; Valiente Feruglio, Gabriel Alejandro (1999-10)
    External research report
    Open Access
    This paper presents a novel approach to the problem of finding all subgraph isomorphisms of a (pattern) graph into another (target) graph. A relational formulation of the problem, combined with a representation of relations ...