Browsing by Author "Palomar Pérez, Óscar"
Now showing items 1-20 of 27
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Advanced pattern based memory controller for FPGA based HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policyThe ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. To address this issue, we propose the Advanced Pattern based Memory Controller (APMC), which ... -
AMMC: advance multi-core memory controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference lecture
Open AccessIn this work, we propose an efficient scheduler and intelligent memory manager known as AMMC (Advanced Multi-Core Memory Controller), which proficiently handles data movement and computational tasks. The proposed AMMC ... -
An integrated vector-scalar design on an in-order ARM core
(2017-07)
Article
Open AccessIn the low-end mobile processor market, power, energy, and area budgets are significantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient ... -
Block-based execution on an integrated vector-scalar in-order core
(Barcelona Supercomputing Center, 2015-05-05)
Conference report
Open AccessIn the low-end processor mobile market, power, energy and area budgets are significantly lower than in the server/desktop/lap-top/high-end mobile markets. It has been shown that vector processors are a highly energy-efficient ... -
DLP acceleration on general purpose cores
(Barcelona Supercomputing Center, 2015-05-05)
Conference report
Open AccessHigh-performance and power-efficient multimedia computing drives the design of modern and increasingly utilized mobile devices. State-of-the-art low power processors already utilize chip multiprocessors (CMP) that add ... -
Dynamic-vector execution on a general purpose EDGE chip multiprocessor
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policyThis paper proposes a cost-effective technique that morphs the available cores of a low power chip multiprocessor (CMP) into an accelerator for data parallel (DLP) workloads. Instead of adding a special-purpose vector ... -
Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Open AccessGraph500 is a data intensive application for high performance computing and it is an increasingly important workload because graphs are a core part of most analytic applications. So far there is no work that examines if ... -
EVX: vector execution on low power EDGE cores
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Conference report
Restricted access - publisher's policyIn this paper, we present a vector execution model that provides the advantages of vector processors on low power, general purpose cores, with limited additional hardware. While accelerating data-level parallel (DLP) ... -
Imposing coarse-grained reconfiguration to general purpose processors
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Conference report
Restricted access - publisher's policyMobile devices execute applications with diverse compute and performance demands. This paper proposes a general purpose processor that adapts the underlying hardware to a given workload. Existing mobile processors need to ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policyTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policyTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
On the selection of adder unit in energy efficient vector processing
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Restricted access - publisher's policyVector processors are a very promising solution for mobile devices and servers due to their inherently energy-efficient way of exploiting data-level parallelism. Previous research on vector architectures predominantly ... -
PAMS: pattern aware memory system for embedded systems
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Conference report
Open AccessIn this paper, we propose a hardware mechanism for embedded multi-core memory system called Pattern Aware Memory System (PAMS). The PAMS supports static and dynamic data structures using descriptors and specialized memory ... -
ParaDIME: Parallel distributed infrastructure for minimization of energy for data centers
(2015-11-01)
Article
Open AccessDramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On the one hand, designers use technology scaling as ... -
Physical vs. physically-aware estimation flow: case study of design space exploration of adders
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Restricted access - publisher's policySelecting an appropriate estimation method for a given technology and design is of crucial interest as the estimations guide future project and design decisions. The accuracy of the estimations of area, timing, and power ... -
POSTER: an integrated vector-scalar design on an in-order ARM core
(Association for Computing Machinery (ACM), 2016)
Conference report
Restricted access - publisher's policyIn the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly ... -
PVMC: Programmable Vector Memory Controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Conference report
Open AccessIn this work, we propose a Programmable Vector Memory Controller (PVMC), which boosts noncontiguous vector data accesses by integrating descriptors of memory patterns, a specialized local memory, a memory manager in hardware, ... -
Reusing cached schedules in an out-of-order processor with in-order issue logic
(2009)
Conference report
Open AccessThe complex and powerful out-of-order issue logic dismisses the repetitive nature of the code, unlike what caches or branch predictors do. We show that 90% of the cycles, the group of instructions selected by the issue ... -
Reusing cached schedules in an out-of-order processor with in-order issue logic
(Universitat Politècnica de Catalunya, 2011-05-09)
Doctoral thesis
Open AccessModern processors use out-of-order processing logic to achieve high performance in Instructions Per Cycle (IPC) but this logic has a serious impact on the achievable frequency. In order to get better performance out of ... -
Runtime-aware architectures
(Springer, 2015)
Conference report
Open AccessIn the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ...
