Now showing items 1-20 of 24

  • A comprehensive compensation technique for process variations and environmental fluctuations in digital integrated circuits 

    Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2010)
    Conference report
    Open Access
    Abstract—Process variability and environmental fluctuations deeply affect the digital circuits performance in many different ways, one of them, the data processing time which may cause error on synchronous digital circuits ...
  • All-digital self-adaptive PVTA variation aware clock generation system for DFS 

    Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (2014)
    Conference report
    Open Access
    An all-digital self-adaptive clock generation system capable of adapt the clock frequency to compensate the effects of PVTA variations on the IC propagation delay and satisfy an externally set propagation length condition ...
  • All-digital simple clock synthesis through a glitch-free variable-length ring oscillator 

    Pérez Puigdemont, Jordi; Moll Echeto, Francisco de Borja; Calomarde Palomino, Antonio (2014-02-01)
    Article
    Restricted access - publisher's policy
    This brief presents a simple all-digital variable-length ring oscillator (VLRO) design that is capable of synchronously changing the output frequency while keeping a signal free of glitches or spurious oscillations at the ...
  • Analysis of delay mismatching of digital circuits caused by common environmental fluctuations 

    Andrade Miceli, Dennis Michael; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Cotofana, Sorin (IEEE, 2011)
    Conference report
    Restricted access - publisher's policy
    Environmental conditions are changing all the time along the chip as a consequence of its own activity, provoking deviations on propagation time in digital circuits. In future technologies, the increment of devices sensitivity ...
  • A new probabilistic design methodology of nanoscale digital circuits 

    García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (IEEE Press. Institute of Electrical and Electronics Engineers, 2011)
    Conference report
    Restricted access - publisher's policy
    The continuing trends of device scaling and increase in complexity towards terascale system on chip level of integration are putting growing difficulties into several areas of design. The intrinsic variability problem is ...
  • A single event transient hardening circuit design technique based on strengthening 

    Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2013)
    Conference report
    Restricted access - publisher's policy
    In a near future of high-density and low-power technologies, the study of soft errors will not only be relevant for memory systems and latches of logic circuits, but also for the combinational parts of logic circuits which ...
  • Closed loop controlled ring oscillator: a variation tolerant self-adaptive clock generation architecture 

    Pérez Puigdemont, Jordi; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja (2012)
    Conference lecture
    Open Access
  • Eines d’autor: avaluació de noves eines orientades al desenvolupament de competències genèriques per la millora del procés d’aprenentatge autònom dels estudiants 

    Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio; Vigara Campmany, Julio Enrique; Romeral Martínez, José Luis; Ortega Redondo, Juan Antonio (Universitat Politècnica de Catalunya. Institut de Ciències de l'Educació, 2013-02-08)
    Conference report / Conference lecture
    Open Access
    Els cursos on-line massius (Massive Open On-line Courses) estan emergent i suposarà un gran repte en l’educació universitària en els propers anys. Universitats com Standford i MIT han començat aquest any cursos en obert ...
  • FinFET and III-V/Ge technology impact on 3T1D cell behavior 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013)
    Conference lecture
    Open Access
    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ...
  • Fundamentos de electrónica 

    Calomarde Palomino, Antonio (Edicions UPC, 2002)
    Book
    Restricted access to the UPC academic community
    En este libro se recogen los conceptos necesarios para cubrir un curso completo de Electrónica. Se empieza con una descripción de los dispositivos fundamentales utilizados en Electrónica (Diodos, transistor bipolar, ...
  • High level spectral-based análisis of power concumption in DSP's systems 

    Calomarde Palomino, Antonio; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Conference report
    Restricted access - publisher's policy
    In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage ...
  • Impact of finfet and III-V/Ge technology on logic and memory cell behavior 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
    Article
    Restricted access - publisher's policy
    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ...
  • New redundant logic design concept for high noise and low voltage scenarios 

    García Leyva, Lancelot; Andrade Miceli, Dennis Michael; Gómez Fernández, Sergio; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2011-12)
    Article
    Restricted access - publisher's policy
    This paper presents a new redundant logia design concept named Turtle Logic(TL).It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, ...
  • Novel redundant logic design for noisy low voltage scenarios 

    García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
    Conference report
    Restricted access - publisher's policy
    The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ...
  • Optimization of FinFET-based gain cells for low power sub-vt embedded drams 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2018-06-01)
    Article
    Open Access
    Sub-threshold circuits (sub-V T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to ...
  • Reliability study on technology trends beyond 20nm 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (Lodz University of Technology, 2013)
    Conference report
    Restricted access - publisher's policy
    In this work, an assessment of different technology trends (planar CMOS, FinFET and III-V MOSFETs) has been carried out in front of some different reliability scenarios (variability and soft errors). The logic circuits ...
  • Review on suitable eDRAM configurations for next nano-metric electronics era 

    Amat, Esteve; Canal Corretger, Ramon; Calomarde Palomino, Antonio; Rubio Sola, Jose Antonio (2018-03)
    Article
    Open Access
    We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform ...
  • Robust sequential circuits design technique for low voltage and high noise scenarios 

    García Leyva, Lancelot; Rivera Dueñas, Juan; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2016)
    Conference report
    Open Access
    All electronic processing components in future deep nanotechnologies will exhibit high noise level and/ or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. ...
  • SET and noise fault tolerant circuit design techniques: application to 7 nm FinFET 

    Calomarde Palomino, Antonio; Amat Bertran, Esteve; Moll Echeto, Francisco de Borja; Vigara Campmany, Julio Enrique; Rubio Sola, Jose Antonio (2014-04-01)
    Article
    Open Access
    In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable ...
  • Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level 

    Amat, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Conference lecture
    Restricted access - publisher's policy
    This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10 nm FinFET devices. The use of ...