Now showing items 1-10 of 10

  • A case study for the verification of complex timed circuits: IPCMOS 

    Peña Basurto, Marco Antonio; Cortadella, Jordi; Pastor Llorens, Enric; Smirnov, Alexandre (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    The verification of a n-stage pulse-driven IPCMOS pipeline, for any n>0, is presented. The complexity of the system is 32n transistors and delay information is provided at the level of transistor The correctness of the ...
  • Automatic generation of synchronous test patterns for asynchronous circuits 

    Roig Mansilla, Oriol; Cortadella, Jordi; Peña Basurto, Marco Antonio; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ...
  • Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits 

    Peña Basurto, Marco Antonio; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1996)
    Conference report
    Open Access
    This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic ...
  • Flujo de diseño asíncrono con la biblioteca DCVSL_LIB para ES2 ECPD10 

    Sintes, L; Escudero Acuña, Javier; Peña Basurto, Marco Antonio; Roig Mansilla, Oriol; Cortadella, Jordi; Carrabina Bordoll, Jordi (Omron, 1996)
    Conference report
    Open Access
    En el presente trabajo se pretende abordar la metodología a seguir durante el flujo de diseño de un circuito asíncrono orientado a prestaciones, utilizando la biblioteca DCVSL_LIB para aplicaciones asíncronas que hemos ...
  • Formal verification of safety properties in timed circuits 

    Peña Basurto, Marco Antonio; Cortadella, Jordi; Kondratyev, Alex; Pastor Llorens, Enric (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Conference report
    Open Access
    The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed stare space, a conservative ...
  • Introducción a la programación en C 

    Peña Basurto, Marco Antonio; Cela Espín, José M. (Edicions UPC, 2000)
    Book
    Restricted access to the UPC academic community
    Texto de introducción a la programación usando el lenguaje C, centrado en la exposición de los aspectos fundamentales del estándar ANSI C actual. Si bien en la actualidad existen otros lenguajes de programación muy populares, ...
  • Partial order based approach to synthesis of speed-independent circuits 

    Semenov, Alex; Yakovlev, Alex; Pastor Llorens, Enric; Peña Basurto, Marco Antonio; Cortadella, Jordi; Lavagno, Luciano (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    This paper introduces a novel technique for synthesis of speed-independent circuits from their Signal Transition Graph specifications. The new method uses partial order in the form of the STG-unfolding segment to derive ...
  • Programación VLSI y síntesis de circuitos asíncronos mediante composición de redes de Petri 

    Peña Basurto, Marco Antonio; Cortadella, Jordi (1995)
    Conference report
    Open Access
    Tangram es un lenguaje de programación VLSI traducible automáticamente a redes de módulos asíncronos llamados componentes de sincronización. En este artículo se usan los Grafos de Transiciones de Señales (STGs) para describir ...
  • Structural methods to improve the symbolic analysis of Petri nets 

    Pastor Llorens, Enric; Cortadella, Jordi; Peña Basurto, Marco Antonio (Springer, 1999)
    Conference report
    Open Access
    Symbolic techniques based on BDDs (Binary Decision Diagrams) have emerged as an efficient strategy for the analysis of Petri nets. The existing techniques for the symbolic encoding of each marking use a fixed set of variables ...
  • Synthesis of speed-independent circuits from STG-unfolding segment 

    Semenov, Alex; Yakovlev, Alex; Pastor Llorens, Enric; Peña Basurto, Marco Antonio; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    This paper presents a novel technique for synthesis of speed-independent circuits. It is based on partial order representation of the state graph called STG-unfolding segment. The new method uses approximation technique ...