Browsing by Author "02182752-aeb6-49a0-a544-70685f0929be;drac:178693;gauss:1000712;orcid:0000-0002-3753-4108"
Now showing items 1-20 of 34
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Analysis and simulation of multiplexed single-bus networks with and without buffering
(Institute of Electrical and Electronics Engineers (IEEE), 1985)
Conference report
Open AccessPerformance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. ... -
Computing size-independent matrix problems on systolic array processors
(Institute of Electrical and Electronics Engineers (IEEE), 1986)
Conference report
Open AccessA methodology to transform dense to band matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of solutions to problems with any given ... -
Computing size-independent matrix problems on systolic array processors
(1985)
Research report
Open AccessA methodology to transform dense to banded matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of silutions to problems with any given ... -
Conflict-free strides for vectors in matched memories
(1991-12)
Article
Open AccessAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these ... -
El optimizador de bucles del compilador Open64/ORC
(2004-12-14)
Research report
Open Access -
El optimizador de bucles del compilador Open64/ORC (parte 2)
(2005-09-05)
Research report
Open AccessOpen64 y ORC (Open Research Compiler) son dos iniciativas de código abierto basadas en el compilador SGI Pro64. Open64 está gestionada por miembros de la Universidad de Delaware, y ORC es una extensión del compilador ... -
Evaluating A+B=K conditions in constant time
(Institute of Electrical and Electronics Engineers (IEEE), 1988)
Conference report
Open AccessThe authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, ... -
Evaluation of A+B=K conditions without carry propagation
(Institute of Electrical and Electronics Engineers (IEEE), 1992-11)
Article
Open AccessThe response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that ... -
Filtering directory lookups in CMPs
(2010)
Conference report
Open AccessCoherence protocols consume an important fraction of power to determine which coherence action should take place. In this paper we focus on CMPs with a shared cache and a directory-based coherence protocol implemented as ... -
Implementation of systolic algorithms using pipelined functional units
(1990)
Conference report
Open AccessThe authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of ... -
Increasing the number of strides for conflict-free vector access
(1992-05)
Article
Open AccessAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ... -
Introducción al compilador Open64/ORC
(2003-05-13)
Research report
Open Access -
Keeping control transfer instructions out of the pipeline in architectures without condition codes
(1987-05)
Research report
Open AccessThe execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ... -
L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime
(Public Library of Science (PLOS), 2023-02-07)
Article
Open AccessSeveral emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but ... -
Leveraging data compression for performance-efficient and long-lasting NVM-based last-level cache
(University of California, Los Angeles (UCLA), 2023)
Conference lecture
Open AccessNon-volatile memory (NVM) technologies are interesting alternatives for building on-chip Last-Level Caches (LLCs). Their advantages, compared to SRAM memory, are higher density and lower static power, but each write operation ... -
MNEMOSENE++: Scalable multi-tile design with enhanced buffering and VGSOT-MRAM based compute-in-memory crossbar array
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Conference lecture
Open AccessThis paper optimizes the MNEMOSENE architecture, a compute-in-memory (CiM) tile design integrating computation and storage for increased efficiency. We identify and address bottlenecks in the Row Data (RD) buffer that cause ... -
Near-optimal replacement policies for shared caches in multicore processors
(2021-10)
Article
Open AccessAn optimal replacement policy that minimizes the miss rate in a private cache was proposed several decades ago. It requires knowing the future access sequence the cache will receive. There is no equivalent for shared caches ... -
On automatic loop data-mapping for distributed-memory multiprocessors
(Springer, 1991)
Conference report
Open AccessIn this paper we present a unified approach for compiling programs for Distributed-Memory Multiprocessors (DMM). Parallelization of sequential programs for DMM is much more difficult to achieve than for shared memory systems ... -
On reducing misspeculations on a pipelined scheduler
(2009)
Conference report
Open AccessPipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance. In a 4-issue processor, our evaluations show that pipelining the scheduling logic over two ... -
Partitioning: an essential step in mapping algorithms into systolic array processors
(1987-07)
Article
Open AccessThe efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size.
