Now showing items 1-20 of 27

  • Analysis and simulation of multiplexed single-bus networks with and without buffering 

    Llaberia Griñó, José M.; Valero Cortés, Mateo; Herrada Lillo, Enrique; Labarta Mancho, Jesús José (Institute of Electrical and Electronics Engineers (IEEE), 1985)
    Conference report
    Open Access
    Performance issues of a single-bus interconnection network for multiprocessor systems, operating in a multiplexed way, are presented in this paper. Several models are developed and used to allow system performance evaluation. ...
  • Computing size-independent matrix problems on systolic array processors 

    Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1985)
    External research report
    Open Access
    A methodology to transform dense to banded matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of silutions to problems with any given ...
  • Computing size-independent matrix problems on systolic array processors 

    Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1986)
    Conference report
    Open Access
    A methodology to transform dense to band matrices is presented in this paper. This transformation, is accomplished by triangular blocks partitioning, and allows the implementation of solutions to problems with any given ...
  • Conflict-free strides for vectors in matched memories 

    Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Navarro Guerrero, Juan José; Ayguadé Parra, Eduard (1991-12)
    Article
    Open Access
    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these ...
  • El optimizador de bucles del compilador Open64/ORC 

    Santamaria Barnadas, Eduard; Jiménez Castells, Marta; Fernández Jiménez, Agustín; Llaberia Griñó, José M. (2004-12-14)
    External research report
    Open Access
  • El optimizador de bucles del compilador Open64/ORC (parte 2) 

    Santamaria Barnadas, Eduard; Jiménez Castells, Marta; Fernández Jiménez, Agustín; Llaberia Griñó, José M. (2005-09-05)
    External research report
    Open Access
    Open64 y ORC (Open Research Compiler) son dos iniciativas de código abierto basadas en el compilador SGI Pro64. Open64 está gestionada por miembros de la Universidad de Delaware, y ORC es una extensión del compilador ...
  • Evaluating A+B=K conditions in constant time 

    Cortadella, Jordi; Llaberia Griñó, José M. (Institute of Electrical and Electronics Engineers (IEEE), 1988)
    Conference report
    Open Access
    The authors consider a type of condition that can be evaluated without requiring a complete ALU (arithmetic logic unit) operation. The circuit that is presented detects the condition A+B=K (n-bit numbers) in constant time, ...
  • Evaluation of A+B=K conditions without carry propagation 

    Cortadella, Jordi; Llaberia Griñó, José M. (Institute of Electrical and Electronics Engineers (IEEE), 1992-11)
    Article
    Open Access
    The response time of parallel adders is mainly determined by the carry propagation delay. The evaluation of conditions of the type A+B=K is addressed. Although an addition is involved in the comparison, it is shown that ...
  • Filtering directory lookups in CMPs 

    Bosque, Ana; Viñals Yufera, Víctor; Ibáñez, Pablo; Llaberia Griñó, José M. (2010)
    Conference report
    Open Access
    Coherence protocols consume an important fraction of power to determine which coherence action should take place. In this paper we focus on CMPs with a shared cache and a directory-based coherence protocol implemented as ...
  • Implementation of systolic algorithms using pipelined functional units 

    Valero García, Miguel; Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1990)
    Conference report
    Open Access
    The authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of ...
  • Increasing the number of strides for conflict-free vector access 

    Valero Cortés, Mateo; Lang, Tomas; Llaberia Griñó, José M.; Peiron Guàrdia, Montse; Ayguadé Parra, Eduard; Navarro Guerrero, Juan José (1992-05)
    Article
    Open Access
    Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ...
  • Introducción al compilador Open64/ORC 

    Santamaria Barnadas, Eduard; Jiménez Castells, Marta; Fernández Jiménez, Agustín; Llaberia Griñó, José M. (2003-05-13)
    External research report
    Open Access
  • Keeping control transfer instructions out of the pipeline in architectures without condition codes 

    Cortadella, Jordi; Llaberia Griñó, José M.; González Colás, Antonio María (1987-05)
    External research report
    Open Access
    The execution of branch instructions involves a loss of performance in pipelined processors. In this paper we present a mechanism for executing this kind of instruction with a zero delay. This mechanism has been proposed ...
  • On reducing misspeculations on a pipelined scheduler 

    Gran Tejero, Ruben; Morancho Llena, Enrique; Olivé Durán, Ángel; Llaberia Griñó, José M. (2009)
    Conference report
    Open Access
    Pipelining the scheduling logic, which exposes and exploits the instruction level parallelism, degrades processor performance. In a 4-issue processor, our evaluations show that pipelining the scheduling logic over two ...
  • Partitioning: an essential step in mapping algorithms into systolic array processors 

    Navarro Guerrero, Juan José; Llaberia Griñó, José M.; Valero Cortés, Mateo (1987-07)
    Article
    Open Access
    The efficient solution of a large problem on a small systolic array requires good partitioning techniques to split the problem into subproblems that fit the array size.
  • ReD: A policy based on reuse detection for demanding block selection in last-level Caches 

    Díaz Maag, Javier; Ibáñez Marín, Pablo Enrique; Monreal Arnal, Teresa; Viñals Yúfera, Víctor; Llaberia Griñó, José M. (2017)
    Conference report
    Open Access
    In this paper, we propose a new block selection policy for Last-Level Caches (LLCs) that decides, based on Reuse Detection, whether a block coming from main memory is inserted, or not, in the LLC. The proposed policy, ...
  • ReD: A reuse detector for content selection in exclusive shared last-level caches 

    Díaz, Javier; Monreal Arnal, Teresa; Ibáñez Marín, Pablo Enrique; Llaberia Griñó, José M.; Viñals Yúfera, Víctor (Elsevier, 2019-03)
    Article
    Restricted access - publisher's policy
    The reference stream reaching a chip multiprocessor Shared Last-Level Cache (SLLC) shows poor temporal locality, making conventional cache management policies inefficient. Few proposals address this problem for exclusive ...
  • Reducción de la degradación y el conflicto en las redes de interconexión para sistemas multiprocesadores 

    Llaberia Griñó, José M.; Labarta Mancho, Jesús José; Herrada Lillo, Enrique; Valero Cortés, Mateo (Asociación Española de Informática y Automática, 1985)
    Conference report
    Open Access
    Uno de los parámetros causante de una disminuación potencial de la eficiencia de un sistema multiprocesador es el tiempo de respuesta del subsistemas de memoria. En este trabajo se presentan diversas técnicas que mejoran ...
  • Reducing branch delay to zero in pipelined processors 

    González Colás, Antonio María; Llaberia Griñó, José M. (1993-03)
    Article
    Open Access
    A mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ...
  • Reuse Detector: improving the management of STT-RAM SLLCs 

    Rodríguez Rodríguez, Roberto; Díaz Maag, Javier; Castro, Fernando; Ibáñez Marín, Pablo Enrique; Chaver Martínez, Daniel A.; Viñals Yúfera, Víctor; Sáez Alcaide, Juan Carlos; Prieto Matías, Manuel; Piñuel, Luis; Monreal Arnal, Teresa; Llaberia Griñó, José M. (2018-06-01)
    Article
    Open Access
    Various constraints of Static Random Access Memory (SRAM) are leading to consider new memory technologies as candidates for building on-chip shared last-level caches (SLLCs). Spin-Transfer Torque RAM (STT-RAM) is currently ...