Exploració per autor "González García, Rubén"
Ara es mostren els items 1-5 de 5
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A content aware integer register file organization
(Institute of Electrical and Electronics Engineers (IEEE), 2004)
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Accés obertA register file is a critical component of a modern superscalar processor. It has a large number of entries and read/write ports in order to enable high levels of instruction parallelism. As a result, the register file's ... -
A decoupled KILO-instruction processor
(Institute of Electrical and Electronics Engineers (IEEE), 2006)
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Accés obertBuilding processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are ... -
A flexible heterogeneous multi-core architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2007)
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Accés obertMulti-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this ... -
A two level load/store queue based on execution locality
(Institute of Electrical and Electronics Engineers (IEEE), 2008)
Text en actes de congrés
Accés obertMulticore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be increasingly limited by the remaining sequential ... -
Chained in-order/out-of-order doublecore architecture
(Institute of Electrical and Electronics Engineers (IEEE), 2005)
Text en actes de congrés
Accés obertComplexity is one of the most important problems facing microarchitects. It is exacerbated by the application of optimizations, by scaling to higher issue widths and, in general, by increasing the size of microprocessor ...
