Enhanced performance controller for high power wind converters connected to weak grids

: This study proposes a control scheme for high power grid-connected wind power converters, which is oriented to enhance their performance when connected to weak grids with low short circuit ratio. The proposed controller consists of an outer current reference generation loop and an inner current loop, working in stationary reference frame. In the outer loop, the current reference is calculated to comply simultaneously with the grid code requirements, the control of the DC link, and the operational safety margins of the converter during faulty conditions. On the other hand, the proposed inner current loop consists of a proportional resonant controller, a capacitor voltage feedforward and a phase shifter. Moreover, simulation results considering different weak grid conditions, as well as experimental results of a full-scale 4 MW converter test-bench are presented to validate the good performance of the proposed method.


Introduction
Nowadays, high power photovoltaic and wind generation power plants play an important role in the electric power system, covering a significant percentage of the power demand [1,2]. Although these green energies have a beneficial environmental impact, the particular dynamics, their lack of inertia and the variability of such plants hinders the stability of the network [3]. As a consequence, the transmission system operators (TSOs) have updated their grid codes and standards setting new and demanding requirements for renewable energy-based power plants under steady-state and transient conditions [4,5] to guarantee a harmonic integration of these plants, whose installation is prone to increase exponentially in the next years. These grid code requirements (GCRs) demand renewable energy source (RES) based power plants to support the network actively during grid faults, injecting positive and negative sequence active and reactive currents during grid faults [6]. These requirements are reflected in the low-voltage ride through (LVRT) requirements issued by the TSOs all over the world [7]. The use of grid feeding voltage source converters is a widespread solution for connecting high power RES-based plants to the grid, due to the good trade-off that such system offers between cost, safe-operation, controllability and dynamic behaviour [8,9]. Since these plants are often located in remote areas, where the grid has low short circuit ratio (SCR), the control of the power conversion systems has a significant influence on the performance of the grid at the point of common coupling (PCC), especially under fault conditions [10,11]. In this regard, two main points should be considered in the design of the control scheme [12]: (i) To define a suitable current reference considering GCR and the converter operation boundaries; (ii) To design an inner current loop able to track the current reference under all grid conditions.
Concerning the first point, several proposals for generating the operation setpoint have been presented based on the development of power control strategies, especially under faulty grid conditions [13,14]. For instance, the works presented in [15,16] proposed different schemes for controlling STATCOMs such as the average active reactive control, the balanced positive sequence control, or the positive negative sequence control (PNSC). Likewise, the flexible positive and negative sequence power control (FPNSC) [17], went one step forward, synthesising current references able to improve the positive sequence voltage profile while minimising the unbalanced voltages produced by the fault. The FPNSC is improved in [18] to avoid using phase locked loop, and it is upgraded in [19] to uniquely determine the current reference by the fault condition and predefined constants from the grid code. The flexible strategy was modified by [20,21] to limit the current reference during severe conditions; however, the proposed solution gives rise to a complex final implementation. The main reason behind this complexity lays on the fact that these methods convert active/reactive power references to current references, which leads to mismatches and complex calculations to define the grid voltage module in faulty conditions.
The defined current reference in the outer loop should be tracked by the inner current loop [22,23], which is the second controller indicated previously. These controllers can be referred to natural abc, synchronous dq0, or stationary αβ0 reference frame components, as finally, all methodologies are mathematically equivalent [24,25]. However, the development and implementation of controllers in the αβ0 reference frame is currently becoming more popular, as the transformations are simple and less costly from a computational point of view [26]. Besides, this reference frame is itself orthogonal and the cross-coupling terms between control axes are cancelled, while these features cannot be found in implementations based on the dq0 axis [27,28].
In addition to control, hardware plays a significant role, even more in high power systems. In most high power grid-connected power converters, LCL filters are considered the preferred interface with the network [27,29]. These filters are designed by choosing the resonance frequency value far from the fundamental frequency. However, in high power converters with low switching frequencies, this value is relatively close to the fundamental frequency, which may lead to instability issues in the inner current loop [30]. To overcome this drawback, two methods are broadly extended for damping the resonance peak: introducing physical passive damping by adding some passive elements to the LCL filter or introducing active damping by changing the structure of the controller to increase the magnitude and phase margins (PMs) around the resonance frequency [31]. However, the implementation of effective active damping is not straightforward [32], and different proposals have been presented in [33,34].
According to the latest changes in the grid codes, during grid faults power plants must inject positive and negative sequence reactive currents based on the voltage profile at the PCC [5,35]. Based on the literature review of authors, a dual control scheme in dq0 was presented in [21] to cover new grid codes; however, this study only presented simulation results and did not consider the practical constraints and resonance issues in real high power converter. Other researches in [7][8][9][10][11][12][13][14][15][16][17][18][19][20] have mainly used power references as interface variable to find out the current references in dq0 and αβ0, but there is a lack of research about implementing the new grid code precisely in αβ0. Moreover, the specific issues associated with the implementation and performance of the control scheme when applied to high power converters have not been carefully addressed yet. In a real case, practical issues such as the delay in the measurement systems, the appearance of resonances in weak grids or the reduced controllability due to the use of low switching frequencies have a significant influence in the control of such converters, especially under faulty and transient conditions.
In this paper, an enhanced control scheme, consisting of an outer current reference generator loop and an inner current loop, both working in the αβ0 domain is proposed for a real 4 MVA high power converter. In the outer loop, instantaneous active and reactive current references are generated. These references are calculated and tailored to fulfil the GCRs. To work in a wellreferenced scenario, the current references will be found considering the constraints of the German grid code VDE-AR-N-4120, which is oriented to set the operation boundaries of gridconnected converters under grid fault conditions. In this controller, the proposed inner loop is based on a proportional resonant (PR) controller combined with a voltage feedforward and a new phase shifter for tracking the current reference. This paper intends to deal with practical issues, the proposed solution will integrate as well an active damping system using a voltage feedforward, which will be proven to be a robust method in case of having grid impedance variations. In addition, the implementation of a phase shifter, able to compensate the delay of measurement transducers, and the improvement of the phase lag related to the voltage feedforward will also be contributions linked to this work. This paper is organised as follows. In Sections 2 and 3, the study case and the description of the proposed control scheme are presented, respectively. In Section 4 the simulation results that permit to analyse the performance of the proposed controller under steady-state and faulty conditions are presented. Likewise, the experimental performance is analysed in Section 5, where results collected in a full-scale 4 MW three-phase wind power converter test-bench are shown. Finally, the conclusions and final discussions that arise from this work are presented in Section 6.

System under study
The schematic diagram depicted in Fig. 1 shows the layout of a typical high power grid side converter (GSC) of a generation system, where the energy source is modelled as an ideal current source.
The grid connection filter of the GSC is designed to limit the harmonic injection, limited by the standards. In many applications, this filter is a low-pass filter implemented following an LC or an LCL structure [33]. In this case, L f and C f are inductance and capacitance of the LC filter, also Z g (r g + sL g ) is equivalent grid impedance. The input of energy at the DC side is modelled as a current source i in , which is variable and unpredictable. The braking resistance R in series with a chopper is used to keep the DC bus voltage below the safety limits. The parameters of the 4 MVA study case are listed in Table 1.

Proposed control strategy
The outline of the proposed control strategy is shown in Fig. 2.
In a nutshell, as the system should be responsive to all kinds of voltage sags, the voltage at the capacitors and the converter's current are measured and considered in the current reference generator, where other elements such as the DC voltage regulation and other references are added. This current reference is generated in the outer loop and then tracked by a PR controller in the inner loop, where a phase shifter and active damping blocks are included.

Outer loop: reference generation
The schematic diagram of the proposed outer loop is shown in Fig. 2. In this scheme, it can be seen that the current reference in the stationary reference frame (SRF) is obtained based on the voltage conditions at the PCC and the DC side. In this loop, a current limiter and anti-saturation blocks are included to guarantee that the operation boundaries of the converter do not affect the stability and performance of the control stage. In the figure, the signals i p ± * and i q ± * are the positive & negative active and the reactive current set-points for the converter, which are converted to the αβ domain to be used as the inputs to the inner loop.
The value of i p + * is produced by the DC bus controller, and it is focused on maintaining the voltage at the DC side. According to the standards, the converter should inject reactive currents to support the grid during faults. In Fig. 2, it is shown how the reactive current reference i q+ is defined based on the voltage drop/ rise at the PCC multiplied by the droop coefficient k v+ [33,35]. The dead-band is implemented according to the requirement of each country, which determines different bandwidths. The value of i q + * is obtained from the addition between the reactive current command I q + * plus i q+ . The i p − * is equal to zero according to the VDE-AR-N 4120.
A similar control characteristic can be adopted for the negative sequence. In this case, the i q − * is determined based on the droop function that is applied to the negative sequence voltage at the PCC.
where V band± is the threshold voltage in which the GSC has to work in voltage supporting mode injecting reactive current to the PCC. Also, Δ V + and V − are equal to 1 − V + and V − , in per unit, respectively. It is worth mentioning that the rate limiter in Fig. 2 is used to reduce the change rate of the active current reference in case of grid faults when the reactive current is increased to support the grid voltage. Depending on the application, the country and the technology this rate limiter may be different.

DC bus controller:
The dynamic model of the DC side is shown in Fig. 3, where P o , P loss , and P in are the output active power of the converter, the power losses and the power input, respectively. V dc0 is the nominal value of DC bus voltage and T v is the delay of the voltage transducer.
In the outer loop, the i p + * is generated by the DC bus controller. The structure of the dc-link voltage controller and the associated power loop is shown in Fig. 3.
In Fig. 3, the control strategy is implemented in per-unit system. P base and I in are the nominal power and the active feedforward current, respectively. The open-loop transfer function of the DC link loop (GHdc ol ) is equal to: where K pdc and K idc are the proportional coefficient and the integral coefficients of the PI controller, respectively. Considering the relatively slow dynamics of the DC link, it is possible to ignore the effect of the transducer in the design of the proportional-integral (PI) controller. Therefore, the open-loop transfer function of the DC link loop can be written as: Then, the closed-loop transfer function of the DC control loop (GHdc cl ) is equal to: The above transfer function reveals that the DC link loop presents a low-pass filtering characteristic, which is an interesting feature for attenuating noisy and high-frequency signals. By choosing K pdc = 4 and K idc = 100, the system becomes stable with a PM of 103°, significantly higher than the 60° considered typically. Likewise, the settling time (t s ) can be found from (6):

Anti-saturation:
The GSC needs a minimum voltage in the DC link for injecting reactive power to the PCC. If the value of the DC link voltage reduces below a certain level, the current controllers can get saturated and over modulation may occur giving rise to harmonic currents. An anti-saturation scheme based on a PI controller was proposed by Neumann et al. [35] to modify the reactive power setpoint and prevent uncontrollability. However, this method is slow and cannot avoid the saturation in transient conditions. In this paper, a new analytical anti-saturation scheme is proposed, based on a reference modifier. The proposed method by authors in [36] can adjust the reactive current reference, according to (7), taking into account the grid conditions and the operation points, with no need to know the grid impedance or the voltage where the maximum phase voltage V imax is equal to V dc / 3.

Current limitation:
During faults, the converter should remain connected to the grid, and its current is not allowed to exceed its maximum value set by the semiconductors. On the other hand, according to the standards, the converter must inject reactive current in the positive and the negative sequences with a pattern like Fig. 2 for voltage support. Therefore, the active component of the positive sequence has to be reduced to limit the converter current. Considering the time domain diagram for the positive and negative sequence of the currents, depicted in Fig. 4, the phasor representation for both can be found as shown in (20) and (21) i where θ + and θ − are the phase of positive and negative sequences, respectively. Then the amplitude of converter current can be found as: where θ +0 and θ −0 are the initial phases. Therefore, in (10) by setting cosθ = 1 the maximum converter current I max can be expressed as follows: As a result, the maximum available active current can be found from (13):

Current reference generation in SRF:
There are different methods to obtain the current reference in the SRF from the active and the reactive components: i p ± * and i q ± * . These strategies require the estimation of the negative-and positive-sequence components of the grid voltage under generic conditions. In this regard, some advanced and robust techniques were suggested to detect grid voltage components, which they can work perfectly under unbalanced and distorted grid voltages. In this paper, a dual second order generalised integrator frequency locked loop (DSOGI-FLL), due to its accuracy and fast response, is used for estimating the magnitude of the symmetrical components of the voltage at the PCC [37].
The following method is based on the instantaneous power theory and FPC [15], where the current set-points in the SRF are found from the active and reactive power set-points based on the following relationship: In these equations, v αβ1 is the fundamental component of the grid voltage. The subscript + and − indicate positive and negative sequences, respectively. Equations (14) and (15) work correct in ideal systems; however, in faulty situations, the amplitude of the voltage, which is at the denominator, can be very small. Therefore, (14) and (15) do not work well in fault situations due to the generation of current references with undesirable high amplitudes. [20,38] tried to solve this drawback by modifying denominator but the solutions are complex to practical implementation. In this paper, the following relationship is proposed to determine the current reference in the SRF: In this method, according to (16) and (17), the current reference is built by using the outputs of a DSOGI-FLL. The main advantage of the proposed method is that the current reference in SRF is directly calculated from active/reactive current set-points without converting to power references, which causes matching with grid codes as much as possible.

Inner current loop
The AC model of the GSC is shown in Fig. 5 where V i (s), V g (s), g i and i(s) are the converter output voltage, the grid voltage, the converter gain (0.5V dc ), and the converter output current, respectively. The delay of computation is modelled by e −sT d , where T d is related to the sampling time. The resistor in series with C f is modelled as r d . In this system, V i and V g are accounted as a control input and a disturbance, respectively. The converter current i is the output of this system. In this converter, the current and the PCC voltage are measured where the delay of the transducers are modelled as first-order low-pass filters. T i = 280 µs and T v = 310 µs are the delay of voltage and current transducers, respectively. In the inner current loop, two functions are performed in addition to the implementation of a PR controller: active resonance damping and system stabilisation by using voltage feedforward and phase shifting.
According to Fig. 5, a PR controller with the following relationship operates as the current controller in the inner loop: where k p , k i , and ω c are the proportional gain, the resonant gain and the resonance bandwidth, respectively. The PR controller is proposed to ensure the steady-state reference tracking performance and the fast dynamic response. A non-pure resonant term with resonance bandwidth ω c = 2 rad/s is used in the PR controller to avoid stability problems that can be associated with the infinite gain at the resonance frequency. Also, the voltage feedforward with coefficient k f is used to improve transient response and to damp unstable dynamics related to the resonances.
To set the parameters of the controller, a set of simplification are performed first. Hence, the system model with voltage feedforward can be simplified as shown in the following: Y i ′(s) = e jϕ c e −sT d s 2 L g C f + C f r g + r d + 1 where V i ′ is the output of the current controller. According to the Routh-Hurwitz stability criterion, if any coefficient of the characteristic equation is zero or negative, the system has at least one root with a non-negative real part and it is unstable. Based on (22) and the Routh-Hurwitz criterion, the voltage feedforward (k f ) gain must be lower than one. However, the exact value for this gain should be determined. To find the proportional coefficient (k p ) of the PR controller, the PM and bandwidth criteria will be used. The crossover frequency f c is set usually to be lower than the 10% of the equivalent switching frequency, considering the effect of highfrequency noise. In turn, the cutoff frequency filter f r is usually designed in the region from 25 to 50% of the equivalent switching frequency to ensure an effective harmonic suppression and an excellent dynamic response. The resonant coefficient (k i ) of the PR controller is selected based on the steady-state error at the fundamental frequency. In Figs By selecting a proportional coefficient and a feedforward gain, the following features would be covered: fast dynamic response, high stability margin and resonance elimination. It can be seen from Fig. 6, in open-loop response, that increasing feedforward gain leads to an increase of bandwidth, but to decrease the PM and the attenuation of the resonance.
The reduction in the PM leads to the creation of a peak around the cutoff frequency in the closed-loop response, as shown in Fig. 7. By increasing the feedforward gain, the magnitude around the cutoff frequency and the resonance frequencies get amplified and dropped off, respectively.
In Fig. 8, the effect of the grid voltage on the converter's current is shown. Therefore, the voltage feedforward can be used to reject disturbances around the fundamental and resonance frequencies.
As it is proven in the plot, by increasing the feedforward gain, the grid voltage will have a significant impact on the converter current. The cutoff frequency is within 200-250 Hz. As a result, the effect of the grid voltage harmonics in the converter's current will be higher in this area.
Therefore, it can be concluded from Figs. 6-8 that the voltage feedforward has a dual behaviour, and it must be selected based on a compromise between stability and resonance elimination. The main constraints for setting the feedforward gain selection are: (i) the system becomes unstable without voltage feedforward due to the occurrence of resonance in locations with low SCRs; (ii) when feedforward gain increases, the peak amplitude of the resonance will be declined. However, by increasing the feedforward gain, some peaks appear around the cutoff frequency in the closed-loop response, due to the reduction of the PM in the open-loop response. Therefore, the best value for the feedforward gain is around 0.5, by taking into account the constraints in the open-loop response, the closed-loop response and the effect of the grid voltage in the current bode diagrams.
To enhance stability, a new phase shifter is proposed in (23) to increase PM and to improve stability: This phase shifter is used between the current controller and the SVPWM module to improve the PM of the system and to damp unstable dynamics. Besides, this phase shifter can be used to compensate for the delays of feedback signals to improve the performance of the overall system. In such a way, the delays of transducers are mitigated by adding a phase shifter to the feedback currents and voltages in Fig. 5. The effect of using phase shifters on the bode diagrams are shown in Figs. 9-11. In the open-loop response, shown in Fig. 9, it can be seen that the phase shifter leads to a small increase of the bandwidth, but the improvement in the PM is significant. It should be mentioned that it does not have any effect on the resonance location. According to Fig. 10, using phase shifter smoothes the magnitude of the closedloop response, removes undesired peaks and improves stability. Also, in Fig. 11, the results display that phase shifter works well and decreases the effect of the grid on converter current around the bandwidth frequency (200 Hz).

Simulation results
This section presents the simulation results derived from four different case studies carried out to evaluate the performance of the proposed control scheme with a weak grid (SCR = 4). The parameters of 4 MVA GSC are listed in Table 1. The nominal dclink voltage of the converter is 1150 VDC. The GSC is connected to the grid through a Dyn1 30/0.69 kV three-phase transformer with a 6% impedance. The maximum acceptable converter current I max is 7200 A (1.5211 p.u.) and V imax is considered V dc / 3 (1.1785 p.u.). The SCR of the grid from the high voltage side of the transformer and X/R of grid impedance are chosen to be 4 and 7, respectively. The active reference power is increased by 160 MW/s rate, and it is decreased immediately by step function due to the limitation of the input power source. The droop coefficients k v± set 2 and V band± is considered to be 0.1 p.u in (1) and (2) according to VDE-AR-N 4120. According to Fig. 1, dynamic braking resistors and a dc chopper installed on the dc bus to help regulate the dc bus voltage during transients and grid faults.
i. Start-up and power reference change at normal grid conditions: The simulation results considering a weak grid with SCR = 4 are shown in Fig. 12. The simulation has three stages: first, start-up until t = 0.1 s; then, increase input power to 4 MW from t = 0.1 s until t = 0.2 s by 160 MW/s rate; finally, the input power decreases to 2 MW immediately at t = 0.3 s. Results presented in Fig. 12g prove that DC bus voltage is regulated around 1150 V during the power variation and also, according to Fig. 12b the current references in αβ reference frame increase and decrease proportionally to input power and they are tracked by the current controller without any overshoot and with zero steady-state error. Figs The negative sequence reactive current setpoint is increased from zero because the fault is balanced. (iii) The positive sequence of active current setpoint is reduced to 0.545 to limit the converter's current.
In this case, a severe fault has occurred at the high voltage side of the transformer; as a result, the voltage of the three phases voltages decrease to 0.2 p.u.. The proposed scheme forces GSC to inject a suitable current to support the grid voltage. Therefore, the voltage at the PCC is compensated to 0.48 p.u. compared to the one measured at the high voltage side of the transformer (see Fig. 13h). According to Fig. 13b, the outer loop generates the current reference in the SRF (two sinusoidal current references) based on the positive and negative sequence of the PCC voltage and the active and reactive current references. The resulting current reference is followed with a zero-steady state error and a suitable transient response. It is worth to remark that the current of the converter has always been below the maximum value, hence within safety margins (see Fig. 13d). DC bus voltage is around 1150 V when the grid is normal, and it is clamped to 1230 V by DC chopper during the fault. Likewise, the voltage of the PCC is unbalanced and distorted similar to the high side of the transformer. As can be seen from Fig. 14b, despite the voltage at the PCC, the proposed outer loop generates the reference currents correctly. The PR controller later tracks this current reference without giving rise to any overshoot or steady-state error, endorsing thus the good performance of the proposed control scheme. It is clear from the current waveforms in Fig. 14d that the peak value 6000 A is below the maximum nominal value. In addition, the grid and the converter currents have satisfactory performance. As can  (Fig. 15h). Fig. 15b shows that the currents in αβ are successively matched to the reference current with minimum distortions and spikes at the PCC voltage. In Fig. 15d, the converter current is sinusoidal without any dc component and its maximum is 5500 A when the voltage sags occur.
The obtained results demonstrate that control scheme can control converter according to recently issued standard especially VDE-AR-N 4120 in normal and faulty situations.

Experimental results
To validate the proposed control strategy and observe its behaviour under different real grid conditions, it was implemented in an experimental setup and tested in the lab. The experimental tests have been carried out in a test-bench built by Ingeteam Power Technology S.A. The test-bench allows testing full converter topology in low voltage (LV, 400 V rms ). The parameters and other hardware data are the same as the ones used in throughout the paper, listed also in Table 1. Two experimental cases have been selected in this validation stage, a non-distorted scenario, where a sudden active power step of 1 MW is performed and a faulty situation consisting of severe three-phase voltage sag. The experimental results obtained in these tests are presented in the following figures that show the transient performances of the two cases under weak grid conditions (SCR = 4). The PR regulator is tuned to provide a fast dynamic response, high stability margin and resonance elimination, as in the simulation study case. In the first test, an active power step of 1 MW is performed and the reactive power reference is set to zero. The phase to phase grid voltages and the currents delivered to the grid, both oscilloscope registers, are shown in Fig. 16. As it can be seen in the figure, the proposed PR controller offers a good response in front of sudden active power step, with minimal overshoot in current and short rise time, about 20-25 ms. There are not any resonance phenomena in voltage and current. The registers captured by the converter control unit are processed and shown in Fig. 17. The results shown in Figs. 17a and b present the current reference and the real measured current in the α and β axes. As can be concluded from the plots, these references are tracked with the good transient response and zero steady-state error. Fig. 17c illustrates the minimal effect on PCC voltage and Fig. 17d confirms the good behaviour with the converter output.
In the second experimental case, a 100% balanced voltage sag in the amplitude of the grid voltage during 0.5 s is emulated. The response of the system in terms of grid voltages and injected currents, depicted in Fig. 18, also includes zoomed captures, Figs. 18c and d, centred around the appearance of the fault.
It can be concluded from the figure when the fault appears, the system has an acceptable transient response with respect to the expected line current overshoot and resonance phenomena. Figs. 19a and b confirm that the reference current is properly followed. As shown in Fig. 19c, the amplitude of the positive sequence in the PCC is reinforced to 0.25 p.u. The power converter by injecting the positive sequence reactive current works supporting the voltage. From Fig. 19d, it can be noted that during the voltage sag, the active power is reduced according to the grid code and, during voltage sag recovery, this output power has a satisfactory response despite being a severe sag. According to the results shown in all the experiments, the good performance of the proposed control strategy has been experimentally validated.

Conclusions
This paper proposes a new control strategy, working in a SRF, to control high power three-phase grid-connected inverter based on two embedded loops: an outer current reference generation loop and an inner current loop. The proposed outer loop generates the current references that comply efficiently with the LVRT requirement of the grid codes, meanwhile protects the converter from operating points that could be harmful for its integrity. The developed inner loop of this paper has proposed a structure that combines PR controllers working in the stationary domain with a phase shifter and active damping blocks. By proposing the voltage feedforward and phase shifter in the control strategy, it can damp the unstable dynamics and improve PM, respectively. Moreover, realistic constraints such as communication delays and signal mismatching have been considered to issue a robust proposal.
The overall structure has been proven to be analytically feasible and effective in the simulation and experimental tests made. In a nutshell, the proposed control permits to generate positive and negative current references that comply with the codes protects the  The simulation and experimental results, obtained using realistic data and parameters, as well as the possibility of testing the proposed system in a real 4 MVA test-bench has permitted to make the most realistic approach, endorsing the validity of the work presented.

Acknowledgment
This work has been partially suported by the Spanish Ministry of Science and Universities under the code RTI2018-100921-B-C21 and Tecniospring programme under the code TECSPR16-1-006.