Exploració per autor "Ayguadé Parra, Eduard"
Ara es mostren els items 168-187 de 326
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MACC: Mercurium ACCelerator Model
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertGPU Offloading is emergent programming model. OpenMP includes in its latest 4.0 specification the accelerator model. In this paper we present a newly implementation of this specification while generationg "native" GPU ... -
Main memory in HPC: do we need more or could we live with less?
(Barcelona Supercomputing Center, 2017-05-04)
Text en actes de congrés
Accés obertThis study analyzes the memory capacity requirements of important HPC benchmarks and applications. We find that the High Performance Conjugate Gradients benchmark could be an important success story for 3D-stacked memories ... -
Main memory in HPC: do we need more, or could we live with less?
(2017-03)
Article
Accés obertAn important aspect of High-Performance Computing (HPC) system design is the choice of main memory capacity. This choice becomes increasingly important now that 3D-stacked memories are entering the market. Compared with ... -
Main memory latency simulation: the missing link
(Association for Computing Machinery (ACM), 2018)
Text en actes de congrés
Accés obertThe community accepted the need for a detailed simulation of main memory. Currently, the CPU simulators are usually coupled with the cycle-accurate main memory simulators. However, coupling CPU and memory simulators is not ... -
Mainstream vs. emerging HPC: metrics, trade-offs and lessons learned
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertVarious servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience ... -
Managing SLAs of heterogeneous workloads using dynamic application placement
(ACM Press, NY, 2008)
Text en actes de congrés
Accés obertIn this paper we address the problem of managing heterogeneous workloads in a virtualized data center. We consider two different workloads: transactional applications and long-running jobs. We present a technique that ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
MAPC: memory access pattern based controller
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialTraditionally, system designers have attempted to improve system performance by scheduling the processing cores and by exploring different memory system configurations and there is comparatively less work done scheduling ... -
Mapping stream programs onto heterogeneous multiprocessor systems
(ACM Press, NY, 2009)
Comunicació de congrés
Accés restringit per política de l'editorialThis paper presents a partitioning and allocation algorithm for an iterative stream compiler, targeting heterogeneous multiprocessors with constrained distributed memory and any communications topology. We introduce a ... -
MASA: a multi-platform architecture for sequence aligners with block pruning
(2016-03-01)
Article
Accés obertBiological sequence alignment is a very popular application in Bioinformatics used routinely worldwide. Many implementations of biological sequence alignment algorithms have been proposed for multicores, GPUs, FPGAs and ... -
Memory controller for vector processor
(Springer, 2018-11)
Article
Accés obertTo manage power and memory wall affects, the HPC industry supports FPGA reconfigurable accelerators and vector processing cores for data-intensive scientific applications. FPGA based vector accelerators are used to increase ... -
MetH: A family of high-resolution and variable-shape image challenges
(2019-11-20)
Report de recerca
Accés obertHigh-resolution and variable-shape images have not yet been properly addressed by the AI community. The approach of down-sampling data often used with convolutional neural networks is sub-optimal for many tasks, and has ... -
Micro-architectural characterization of Apache Spark on batch and stream processing workloads
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialWhile cluster computing frameworks are continuously evolving to provide real-time data analysis capabilities, Apache Spark has managed to be at the forefront of big data analytics for being a unified framework for both, ... -
Mirs: modulo scheduling with integrated register spilling
(2003-01)
Article
Accés restringit per política de l'editorialThe overlapping of loop iterations in software pipelining techniques imposes high register requirements. The schedule for a loop is valid if it requires at most the number of registers available in the target architecture. ... -
Mitigating the NUMA effect on task-based runtime systems
(Springer Nature, 2023-09)
Article
Accés obertProcessors with multiple sockets or chiplets are becoming more conventional. These kinds of processors usually expose a single shared address space. However, due to hardware restrictions, they adopt a NUMA approach, where ... -
Modeling multi-board communication in the AXIOM cyber-physical system
(2016-12-01)
Article
Accés restringit per política de l'editorialThe main goal of the AXIOM project is to design a small board that could be used as a LEGOTM-style module to build systems with more performance while keeping the programming task simple by using a familiar shared-memory ... -
Modulo scheduling with integrated register spilling for clustered VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2001)
Text en actes de congrés
Accés obertClustering is a technique to decentralize the design of future wide issue VLIW cores and enable them to meet the technology constraints in terms of cycle time, area and power dissipation. In a clustered design, registers ... -
Modulo scheduling with reduced register pressure
(1998-06)
Article
Accés obertSoftware pipelining is a scheduling technique that is used by some product compilers in order to expose more instruction level parallelism out of innermost loops. Module scheduling refers to a class of algorithms for ... -
Multimedia big data computing for in-depth event analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés obertWhile the most part of ”big data” systems target text-based analytics, multimedia data, which makes up about 2/3 of internet traffic, provide unprecedented opportunities for understanding and responding to real world ... -
Multiple target task sharing support for the OpenMP accelerator model
(Springer, 2016)
Text en actes de congrés
Accés obertThe use of GPU accelerators is becoming common in HPC platforms due to the their effective performance and energy efficiency. In addition, new generations of multicore processors are being designed with wider vector units ...
