Exploració per autor "Ayguadé Parra, Eduard"
Ara es mostren els items 139-158 de 326
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Hardware-software coherence protocol for the coexistence of caches and local memories
(2015-01-01)
Article
Accés obertCache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce ... -
Heuristics for register-constrained software pipelining
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
Text en actes de congrés
Accés obertSoftware Pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. There has been a significant effort to produce throughput-optimal ... -
Hierarchical clustered register file organization for VLIW processors
(IEEE Computer Society, 2003)
Text en actes de congrés
Accés obertTechnology projections indicate that wire delays will become one of the biggest constraints in future microprocessor designs. To avoid long wire delays and therefore long cycle times, processor cores must be partitioned ... -
Hierarchical task-based programming with StarSs
(2009-08)
Article
Accés restringit per política de l'editorialProgramming models for multicore and many-core systems are listed as one of the main challenges in the near future for computing research. These programming models should be able to exploit the underlying platform, but ... -
How data volume affects spark based data analytics on a scale-up server
(Springer, 2015)
Text en actes de congrés
Accés restringit per política de l'editorialSheer increase in volume of data over the last decade has triggered research in cluster computing frameworks that enable web enterprises to extract big insights from big data. While Apache Spark is gaining popularity for ... -
HPC benchmarking: scaling right and looking beyond the average
(Springer, 2018)
Text en actes de congrés
Accés obertDesigning a balanced HPC system requires an understanding of the dominant performance bottlenecks. There is as yet no well established methodology for a unified evaluation of HPC systems and workloads that quantifies the ... -
Hybrid access-specific software cache techniques for the cell BE architecture
(Association for Computing Machinery, 2008)
Comunicació de congrés
Accés restringit per política de l'editorialEase of programming is one of the main impediments for the broad acceptance of multi-core systems with no hardware support for transparent data transfer between local and global memories. Software cache is a robust approach ... -
Hypernode reduction modulo scheduling
(Institute of Electrical and Electronics Engineers (IEEE), 1995)
Text en actes de congrés
Accés obertSoftware pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution ... -
Impact of the memory hierarchy on shared memory architectures in multicore programming models
(IEEE Computer Society Publications, 2009)
Comunicació de congrés
Accés obertMany and multicore architectures put a big pressure in parallel programming but gives a unique opportunity to propose new programming models that automatically exploit the parallelism of these architectures. OpenMP is a ... -
Impact on performance of fused multiply-add units in aggressive VLIW architectures
(Institute of Electrical and Electronics Engineers (IEEE), 1999)
Text en actes de congrés
Accés obertLoops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the resources offered by the architecture. ... -
Implementation of a high-accuracy phase unwrapping algorithm using parallel-hybrid programming approach for displacement sensing using self-mixing interferometry
(2021-09)
Article
Accés obertPhase unwrapping is an integral part of multiple algorithms with diverse applications. Detailed phase unwrapping is also necessary for achieving high-accuracy metric sensing using laser feedback-based self-mixing interferometry ... -
Implementing OmpSs support for regions of data in architectures with multiple address spaces
(ACM, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe need for features for managing complex data accesses in modern programming models has increased due to the emerging hardware architectures. HPC hardware has moved towards clusters of accelerators and/or multicores, ... -
Improving the integration of task nesting and dependencies in OpenMP
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertThe tasking model of OpenMP 4.0 supports both nesting and the definition of dependences between sibling tasks. A natural way to parallelize many codes with tasks is to first taskify the high-level functions and then to ... -
Improving web server performance through main memory compression
(IEEE Computer Society, 2008)
Comunicació de congrés
Accés obertCurrent web servers are highly multithreaded applications whose scalability benefits from the current multicore/multiprocessor trend. However, some workloads can not capitalize on this because their performance is limited by ... -
Increasing the number of strides for conflict-free vector access
(1992-05)
Article
Accés obertAddress transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free vector access for some strides in vector processors with multi-module memories. In this paper, we ... -
Instrumentation environment for Java threaded applications
(XI Jornadas de Paralelismo, 2000)
Text en actes de congrés
Accés restringit per política de l'editorialThe rapid maturing process of the Java technology is encouraging users to develope of portable applications using the Java language. As an important part of the definition of the Java language, the use of threads is becoming ... -
Integrating dataflow abstractions into the shared memory model
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialIn this paper we present Atomic Dataflow model (ADF), a new task-based parallel programming model for C/C++ which integrates dataflow abstractions into the shared memory programming model. The ADF model provides pragma ... -
Integrating dataflow abstractions into transactional memory
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialMany concurrent programs require some form of conditional synchronization to coordinate the execution of different program tasks. Programming these algorithms using transactional memory (TM) often results in a high ... -
Introducing speculative optimizations in task dataflow with language extensions and runtime support
(2012)
Text en actes de congrés
Accés obertWe argue that speculation leads to increased parallelism in the coarse-grain dataflow paradigm. To do so, we present a framework for adding speculation in a popular and well-established framework. We specify a limited ... -
Is the schedule clause really necessary in OpenMP?
(2003-06)
Article
Accés obertChoosing the appropriate assignment of loop iterations to threads is one of the most important decisions that need to be taken when parallelizing Loops, the main source of parallelism in numerical applications. This is not ...
