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dc.contributor.authorPetura, Oto
dc.contributor.authorMureddu, Ugo
dc.contributor.authorBochard, Nathalie
dc.contributor.authorFischer, Viktor
dc.contributor.authorBossuet, Lilian
dc.coverage.spatialeast=2.11563799999999; north=41.38479239999999; name=Zona Universitària-Escola T S d'Enginyers, 08028 Barcelona, Espanya
dc.date.accessioned2017-01-13T10:39:38Z
dc.date.available2017-01-13T10:39:38Z
dc.date.issued2016-11-14
dc.identifier.urihttp://hdl.handle.net/2117/99207
dc.description.abstractFPGAs are widely used to integrate cryptographic primitives, algorithms, and protocols in cryptographic systemson- chip (CrySoC). As a building block of CrySoCs, True Random Number Generators (TRNGs) exploit analog noise sources in electronic devices to generate confidential keys, initialization vectors, challenges, nonces, and random masks in cryptographic protocols. TRNGs aimed at cryptographic applications must fulfill the security requirements defined in the German Federal Bureau for Information Security’s (BSI) recommendations AIS- 20/31, which has become a de facto standard in Europe. Many TRNG cores have already been published, only a few of which are suitable for FPGAs and even fewer comply with AIS-20/31. Here we present the results of the implementation of AIS-20/31 compliant TRNG cores in three FPGA families: Xilinx Spartan 6, Altera Cyclone V and Microsemi SmartFusion 2. In addition to common design parameters like area, bit rate and power/energy consumption, we compare and discuss the feasibility of generator cores in different FPGAs and the statistical quality of their output. These results will help designers select the best generator and the device family to match the requirements of the data security application. To ensure reproducibility of the results, the open source VHDL code of all generators adapted to individual families can be downloaded from the dedicated web page.
dc.format.extent6 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshEmbedded computer systems--Congresses
dc.subject.lcshIntegrated circuits
dc.subject.lcshComputer networks--Security measures
dc.titleEvaluation of AIS-20/31 compliant TRNG cores implemented on FPGAs
dc.typeConference report
dc.subject.lemacSistemes integrats -- Congressos
dc.subject.lemacCircuits integrats
dc.subject.lemacSeguretat informàtica -- Congressos
dc.rights.accessOpen Access
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/644052/EU/HARDWARE ENABLED CRYPTO AND RANDOMNESS/HECTOR


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