Hypernode reduction modulo scheduling
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Software pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations. Most prior scheduling research has focused on achieving minimum execution time, without regarding register requirements. Most strategies tend to stretch operand lifetimes because they schedule some operations too early or too late. The paper presents a novel strategy that simultaneously schedules some operations late and other operations early, minimizing all the stretchable dependencies and therefore reducing the registers required by the loop. The key of this strategy is a pre-ordering that selects the order in which the operations will be scheduled. The results show that the method described in this paper performs better than other heuristic methods and almost as well as a linear programming method but requiring much less time to produce the schedules.
CitacióLlosa, J., Valero, M., Ayguadé, E., González, A. Hypernode reduction modulo scheduling. A: Annual IEEE/ACM International Symposium on Microarchitecture. "Proceedings of the 28th Annual International Symposium on Microarchitecture: November 29-December 1,1995, Ann Arbor, Michigan". Michigan: Institute of Electrical and Electronics Engineers (IEEE), 1995, p. 350-360.
Versió de l'editorhttp://ieeexplore.ieee.org/document/476844/