Fuse: A technique to anticipate failures due to degradation in ALUs
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (arithmetic logic unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the adder appears, and hence, data corruption and program crashes can be avoided. Our results show that the fuse anticipates the failure in more than 99.9% of the cases after 96.6% of the lifetime, even for pessimistic random within-die variations.
CitacióAbella, J., Vera, X., Unsal, O., Ergin, O., González, A. Fuse: A technique to anticipate failures due to degradation in ALUs. A: IEEE International On-Line Testing Symposium. "IOLTS 2007: 13th IEEE International On-Line Testing Symposium: Heraklion, Crete, Greece 8–11 July 2007: proceedings". Hersonissos-Heraklion, Crete: Institute of Electrical and Electronics Engineers (IEEE), 2007, p. 15-22.
Versió de l'editorhttp://ieeexplore.ieee.org/document/4274815/