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Error probability in synchronous digital circuits due to power supply noise
dc.contributor.author | Martorell Cid, Ferran |
dc.contributor.author | Pons, M |
dc.contributor.author | Rubio Sola, Jose Antonio |
dc.contributor.author | Moll Echeto, Francisco de Borja |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2010-10-13T09:12:18Z |
dc.date.available | 2010-10-13T09:12:18Z |
dc.date.created | 2007 |
dc.date.issued | 2007 |
dc.identifier.citation | Martorell, F. [et al.]. Error probability in synchronous digital circuits due to power supply noise. A: International Conference on Design and Test of Integrated Circuits in Nanoscale Technology. "International Conference on Design and Test of Integrated Circuits in Nanoscale Technology". Rabat: ???, 2007, p. 170-175. |
dc.identifier.isbn | 978-1-4244-1278-5 |
dc.identifier.uri | http://hdl.handle.net/2117/9653 |
dc.description.abstract | This paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | ??? |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Metal oxide semiconductors, Complementary |
dc.subject.lcsh | Electronics |
dc.subject.lcsh | Integrated circuits--Very large scale integration |
dc.title | Error probability in synchronous digital circuits due to power supply noise |
dc.type | Conference report |
dc.subject.lemac | Electrònica |
dc.contributor.group | Universitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions |
dc.identifier.doi | 10.1109/DTIS.2007.4449513 |
dc.relation.publisherversion | http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4449513 |
dc.rights.access | Open Access |
local.identifier.drac | 2440735 |
dc.description.version | Postprint (published version) |
local.citation.author | Martorell, F.; Pons, M.; Rubio, J.; Moll, F. |
local.citation.contributor | International Conference on Design and Test of Integrated Circuits in Nanoscale Technology |
local.citation.pubplace | Rabat |
local.citation.publicationName | International Conference on Design and Test of Integrated Circuits in Nanoscale Technology |
local.citation.startingPage | 170 |
local.citation.endingPage | 175 |