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dc.contributor.authorMartorell Cid, Ferran
dc.contributor.authorPons, M
dc.contributor.authorRubio Sola, Jose Antonio
dc.contributor.authorMoll Echeto, Francisco de Borja
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.date.accessioned2010-10-13T09:12:18Z
dc.date.available2010-10-13T09:12:18Z
dc.date.created2007
dc.date.issued2007
dc.identifier.citationMartorell, F. [et al.]. Error probability in synchronous digital circuits due to power supply noise. A: International Conference on Design and Test of Integrated Circuits in Nanoscale Technology. "International Conference on Design and Test of Integrated Circuits in Nanoscale Technology". Rabat: ???, 2007, p. 170-175.
dc.identifier.isbn978-1-4244-1278-5
dc.identifier.urihttp://hdl.handle.net/2117/9653
dc.description.abstractThis paper presents a probabilistic approach to model the problem of power supply voltage fluctuations. Error probability calculations are shown for some 90-nm technology digital circuits. The analysis here considered gives the timing violation error probability as a new design quality factor in front of conventional techniques that assume the full perfection of the circuit. The evaluation of the error bound can be useful for new design paradigms where retry and self-recovering techniques are being applied to the design of high performance processors. The method here described allows to evaluate the performance of these techniques by means of calculating the expected error probability in terms of power supply distribution quality.
dc.format.extent6 p.
dc.language.isoeng
dc.publisher???
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshMetal oxide semiconductors, Complementary
dc.subject.lcshElectronics
dc.subject.lcshIntegrated circuits--Very large scale integration
dc.titleError probability in synchronous digital circuits due to power supply noise
dc.typeConference report
dc.subject.lemacElectrònica
dc.contributor.groupUniversitat Politècnica de Catalunya. HIPICS - Grup de Circuits i Sistemes Integrats d'Altes Prestacions
dc.identifier.doi10.1109/DTIS.2007.4449513
dc.relation.publisherversionhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4449513
dc.rights.accessOpen Access
drac.iddocument2440735
dc.description.versionPostprint (published version)
upcommons.citation.authorMartorell, F.; Pons, M.; Rubio, J.; Moll, F.
upcommons.citation.contributorInternational Conference on Design and Test of Integrated Circuits in Nanoscale Technology
upcommons.citation.pubplaceRabat
upcommons.citation.publishedtrue
upcommons.citation.publicationNameInternational Conference on Design and Test of Integrated Circuits in Nanoscale Technology
upcommons.citation.startingPage170
upcommons.citation.endingPage175
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