This paper presents a probabilistic approach to model
the problem of power supply voltage fluctuations. Error
probability calculations are shown for some 90-nm technology
digital circuits. The analysis here considered gives the
timing violation error probability as a new design quality
factor in front of conventional techniques that assume the
full perfection of the circuit. The evaluation of the error
bound can be useful for new design paradigms where retry
and self-recovering techniques are being applied to the design
of high performance processors. The method here described
allows to evaluate the performance of these techniques
by means of calculating the expected error probability
in terms of power supply distribution quality.
CitationMartorell, F. [et al.]. Error probability in synchronous digital circuits due to power supply noise. A: International Conference on Design and Test of Integrated Circuits in Nanoscale Technology. "International Conference on Design and Test of Integrated Circuits in Nanoscale Technology". Rabat: ???, 2007, p. 170-175.
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