On-chip noise generation and coupling is an
important issue in deep-submicron technologies.
Advanced IC technology faces new challenges to
ensure function and performance integrity.
Selecting adequate test techniques depends on
the circuit, its implementation, and the possible
physical failures and parasitic coupling models.
This new demand for test technology practices
precipitated the investigation of dI/dt and dV/dt
noise generation and propagation mechanisms.
CitationAragones, X. [et al.]. Noise generation and coupling mechanisms in deep-submicron IC's. "IEEE design and test of computers", Setembre 2002, vol. 19, núm. 5, p. 27-35.
All rights reserved. This work is protected by the corresponding intellectual and industrial property rights. Without prejudice to any existing legal exemptions, reproduction, distribution, public communication or transformation of this work are prohibited without permission of the copyright holder. If you wish to make any use of the work not provided for in the law, please contact: email@example.com