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dc.contributor.authorVillavieja Prados, Carlos
dc.contributor.authorGelado Fernandez, Isaac
dc.contributor.authorRamírez Bellido, Alejandro
dc.contributor.authorNavarro, Nacho
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2010-09-28T10:55:06Z
dc.date.available2010-09-28T10:55:06Z
dc.date.created2008-06-04
dc.date.issued2008-06-04
dc.identifier.citationVillavieja, C. [et al.]. On-Chip memories, the OS perspective. A: HiPEAC Industrial Workshop. "5th HiPEAC Industrial Workshop. Tools and Methodology for Parallel Programming". Barcelona: 2008, p. 1-2.
dc.identifier.urihttp://hdl.handle.net/2117/9125
dc.description.abstractThis paper is a work in progress study of the operating system services required to manage on-chip memories. We are evaluating different CMP on-chip memories configurations. Chip-MultiProcessors (CMP) architectures integrating multiple computing and memory elements presents different problems (coherency, latency, ...) that must be solved. On-chip local memories are directly addressable and their latency is much shorter than off-chip main memories. Since memory latency is a key factor for application performance, we study how the OS can help.
dc.format.extent2 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMemory management (Computer science)
dc.subject.otherOn-chip memories
dc.subject.otherMemory architecture
dc.titleOn-Chip memories, the OS perspective
dc.typeConference report
dc.subject.lemacGestió de memòria (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.relation.publisherversionhttp://www.hipeac.net/industry_workshop5
dc.rights.accessOpen Access
local.identifier.drac2377723
dc.description.versionPostprint (author’s final draft)
local.citation.authorVillavieja, C.; Gelado, I.; Ramirez, A.; Navarro, N.
local.citation.contributorHiPEAC Industrial Workshop
local.citation.pubplaceBarcelona
local.citation.publicationName5th HiPEAC Industrial Workshop. Tools and Methodology for Parallel Programming
local.citation.startingPage1
local.citation.endingPage2


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