This paper is a work in progress study of the operating system services required to manage on-chip memories. We are evaluating
different CMP on-chip memories configurations. Chip-MultiProcessors (CMP) architectures integrating multiple computing and memory elements presents different problems (coherency, latency, ...) that must be solved. On-chip local memories are directly addressable and their latency is much shorter than off-chip main memories. Since memory latency is a key factor for application performance, we study how the OS can help.
CitacióVillavieja, C. [et al.]. On-Chip memories, the OS perspective. A: HiPEAC Industrial Workshop. "5th HiPEAC Industrial Workshop. Tools and Methodology for Parallel Programming". Barcelona: 2008, p. 1-2.