CATA: Criticality aware task acceleration for multicore processors
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Managing criticality in task-based programming models opens a wide range of performance and power optimization opportunities in future manycore systems. Criticality aware task schedulers can benefit from these opportunities by scheduling tasks to the most appropriate cores. However, these schedulers may suffer from priority inversion and static binding problems that limit their expected improvements. Based on the observation that task criticality information can be exploited to drive hardware reconfigurations, we propose a Criticality Aware Task Acceleration (CATA) mechanism that dynamically adapts the computational power of a task depending on its criticality. As a result, CATA achieves significant improvements over a baseline static scheduler, reaching average improvements up to 18.4% in execution time and 30.1% in Energy-Delay Product (EDP) on a simulated 32-core system. The cost of reconfiguring hardware by means of a software-only solution rises with the number of cores due to lock contention and reconfiguration overhead. Therefore, novel architectural support is proposed to eliminate these overheads on future manycore systems. This architectural support minimally extends hardware structures already present in current processors, which allows further improvements in performance with negligible overhead. As a consequence, average improvements of up to 20.4% in execution time and 34.0% in EDP are obtained, outperforming state-of-the-art acceleration proposals not aware of task criticality.
CitacióCastillo, E., Moreto, M., Casas, M., Álvarez, Ll., Vallejo, E., Chronaki, K., Badia, R.M., Bosque, J., Beivide, R., Ayguadé, E., Labarta, J., Valero, M. CATA: Criticality aware task acceleration for multicore processors. A: IEEE International Parallel and Distributed Processing Symposium. "IPDPS 2016: 2016 IEEE 30th International Parallel and Distributed Processing Symposium: proceedings". Chicago, Illinois: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 413-422.
Versió de l'editorhttp://ieeexplore.ieee.org/document/7516037/