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Predictive runtime code scheduling for heterogeneous architectures
dc.contributor.author | Jimenez, Victor |
dc.contributor.author | Vilanova, Lluis |
dc.contributor.author | Gelado Fernandez, Isaac |
dc.contributor.author | Gil, Marisa |
dc.contributor.author | Fursin, Gregori |
dc.contributor.author | Navarro, Nacho |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2010-09-22T10:19:47Z |
dc.date.available | 2010-09-22T10:19:47Z |
dc.date.created | 2009 |
dc.date.issued | 2009 |
dc.identifier.citation | Jimenez, V. [et al.]. Predictive runtime code scheduling for heterogeneous architectures. A: International Conference on High Performance Embedded Architectures and Compilers. "4th International Conference on High Performance Embedded Architectures and Compilers". Paphos: 2009, p. 19-33. |
dc.identifier.isbn | 978-3-540-92989-5 |
dc.identifier.uri | http://hdl.handle.net/2117/9017 |
dc.description.abstract | Heterogeneous architectures are currently widespread. With the advent of easy-to-program general purpose GPUs, virtually every re- cent desktop computer is a heterogeneous system. Combining the CPU and the GPU brings great amounts of processing power. However, such architectures are often used in a restricted way for domain-speci c appli- cations like scienti c applications and games, and they tend to be used by a single application at a time. We envision future heterogeneous com- puting systems where all their heterogeneous resources are continuously utilized by di erent applications with versioned critical parts to be able to better adapt their behavior and improve execution time, power con- sumption, response time and other constraints at runtime. Under such a model, adaptive scheduling becomes a critical component. In this paper, we propose a novel predictive user-level scheduler based on past performance history for heterogeneous systems. We developed sev- eral scheduling policies and present the study of their impact on system performance. We demonstrate that such scheduler allows multiple appli- cations to fully utilize all available processing resources in CPU/GPU- like systems and consistently achieve speedups ranging from 30% to 40% compared to just using the GPU in a single application mode. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació |
dc.subject.lcsh | Graphics processing units |
dc.subject.lcsh | Signal theory (Telecommunication) |
dc.title | Predictive runtime code scheduling for heterogeneous architectures |
dc.type | Conference report |
dc.subject.lemac | Senyal, Teoria del (Telecomunicació) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.rights.access | Open Access |
local.identifier.drac | 2377725 |
dc.description.version | Postprint (published version) |
local.citation.author | Jimenez, V.; Vilanova, L.; Gelado, I.; Gil, Marisa; Fursin, Gregori.; Navarro, N. |
local.citation.contributor | International Conference on High Performance Embedded Architectures and Compilers |
local.citation.pubplace | Paphos |
local.citation.publicationName | 4th International Conference on High Performance Embedded Architectures and Compilers |
local.citation.startingPage | 19 |
local.citation.endingPage | 33 |