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Títol: Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits
Autor: García Leyva, Lancelot
Calomarde Palomino, Antonio
Moll Echeto, Francisco de Borja
Rubio Sola, Jose Antonio
Altres autors/autores: Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica; Universitat Politècnica de Catalunya. HIPICS - Grupo de Circuitos y Sistemas Integrados de Altas Prestaciones
Editorial: IEEE Press. Institute of Electrical and Electronics Engineers
Matèries: Àrees temàtiques de la UPC::Enginyeria electrònica i telecomunicacions::Circuits electrònics
Nanoscale electronic devices
Circuits digitals -- Disseny
Tipus de document: Conference report
Descripció: As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.
Peer Reviewed
Postprint (published version)
Altres identificadors i accés: García, L. [et al.]. Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits. A: IEEE international Midwest Symposium on Circuits and Systems. "53rd IEEE international Midwest Symposium on Circuits and Systems". Seattle, WA,: IEEE Press. Institute of Electrical and Electronics Engineers, 2010, p. 1101-1104.
Disponible al dipòsit:E-prints UPC

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