A bit-level description of the signal processing stage of an on-board integrated VLSI multi-carrier demodulator is presented in this paper, along with a description of the optimization procedure that has been developed for the signal processing functions1. The demultiplexer is capable of handling a varying number of carriers in a 36 MHz bandwidth on the satellite up-link. Its architecture has been optimized at bit-level in a way dependent on the known input signal statistics and carrier distributions allowed by the frequency plan.
CitacióSala, J., Pages, A., Vazquez, G. Efficient bit-level design of an on-board digital TV demultiplexer. A: European Signal Processing Conference. "EUSIPCO 1998: Signal processing IX: theories and applications; proceedings of Eusipco-98, Ninth European Signal Processing Conference: Rhodes, Greece: 8-11 September 1998". Rhodes: 1998, p. 885-889.