High-Level Debugging and Verification for FPGA-Based Multicore Architectures
Tipus de documentComunicació de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Simulators are key tools for computer architecture research. However, multicore architectures represent a highly complex challenge for software simulators, which may suffer from fidelity loss and long execution times. FPGAs can simulate multicore architectures with scalable performance and high accuracy, but the difficulty of debugging could hinder their adoption. In this paper we propose several techniques for inspection, debugging and verification of multicore architectures, both for software-based and FPGA-based simulations. These debugging extensions are cycle-accurate and unobtrusive. As a proof of concept, we have developed a 24-core RISC multiprocessor that runs the Linux Kernel, for which we provide three simulation modes: a fast, functional simulation; a detailed, cycle-accurate simulation; and a FPGA-based simulation. Our platform can run up to 24 cores and perform full-system verification at 17 million instructions per second.
CitacióArcas, Oriol; Cristal, Adrian; Unsal, Osman S. High-Level Debugging and Verification for FPGA-Based Multicore Architectures. A: 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, BC, 2-6 May 2015. "Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on". Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 135-142.