Mostra el registre d'ítem simple

dc.contributor.authorJaulmes, Luc
dc.contributor.authorCasas, Marc
dc.contributor.authorMoretó Planas, Miquel
dc.contributor.authorAyguadé Parra, Eduard
dc.contributor.authorLabarta Mancho, Jesús José
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.contributor.otherBarcelona Supercomputing Center
dc.date.accessioned2016-07-05T08:16:54Z
dc.date.available2016-07-05T08:16:54Z
dc.date.issued2015
dc.identifier.citationJaulmes, L., Casas, M., Moreto, M., Ayguadé, E., Labarta, J., Valero, M. Exploiting asynchrony from exact forward recovery for DUE in iterative solvers. A: International Conference for High Performance Computing, Networking, Storage and Analysis. "Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC 2015)". Austin, TX: Association for Computing Machinery (ACM), 2015, p. 53:1-53:12.
dc.identifier.isbn978-1-4503-3723-6
dc.identifier.urihttp://hdl.handle.net/2117/88494
dc.description.abstractThis paper presents a method to protect iterative solvers from Detected and Uncorrected Errors (DUE) relying on error detection techniques already available in commodity hardware. Detection operates at the memory page level, which enables the use of simple algorithmic redundancies to correct errors. Such redundancies would be inapplicable under coarse grain error detection, but become very powerful when the hardware is able to precisely detect errors. Relations straightforwardly extracted from the solver allow to recover lost data exactly. This method is free of the overheads of backwards recoveries like checkpointing, and does not compromise mathematical convergence properties of the solver as restarting would do. We apply this recovery to three widely used Krylov subspace methods, CG, GMRES and BiCGStab, and their preconditioned versions. We implement our resilience techniques on CG considering scenarios from small (8 cores) to large (1024 cores) scales, and demonstrate very low overheads compared to state-of-the-art solutions. We deploy our recovery techniques either by overlapping them with algorithmic computations or by forcing them to be in the critical path of the application. A trade-off exists between both approaches depending on the error rate the solver is suffering. Under realistic error rates, overlapping decreases overheads from 5.37% down to 3.59% for a non-preconditioned CG on 8 cores.
dc.description.sponsorshipThis work has been partially supported by the European Research Council under the European Union's 7th FP, ERC Advanced Grant 321253, and by the Spanish Ministry of Science and Innovation under grant TIN2012-34557. L. Jaulmes has been partially supported by the Spanish Ministry of Education, Culture and Sports under grant FPU2013/06982. M. Moreto has been partially supported by the Spanish Ministry of Economy and Competitiveness under Juan de la Cierva postdoctoral fellowship JCI-2012-15047. M. Casas has been partially supported by the Secretary for Universities and Research of the Ministry of Economy and Knowledge of the Government of Catalonia and the Co-fund programme of the Marie Curie Actions of the European Union's 7th FP (contract 2013 BP B 00243).
dc.language.isoeng
dc.publisherAssociation for Computing Machinery (ACM)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshError-correcting codes (Information theory)
dc.titleExploiting asynchrony from exact forward recovery for DUE in iterative solvers
dc.typeConference report
dc.subject.lemacCodis correctors d'errors (Teoria de la informació)
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.identifier.doi10.1145/2807591.2807599
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://dl.acm.org/citation.cfm?doid=2807591.2807599
dc.rights.accessOpen Access
local.identifier.drac17530716
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/321253/EU/Riding on Moore's Law/ROMOL
local.citation.authorJaulmes, L.; Casas, M.; Moreto, M.; Ayguadé, E.; Labarta, J.; Valero, M.
local.citation.contributorInternational Conference for High Performance Computing, Networking, Storage and Analysis
local.citation.pubplaceAustin, TX
local.citation.publicationNameProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC 2015)
local.citation.startingPage53:1
local.citation.endingPage53:12


Fitxers d'aquest items

Thumbnail

Aquest ítem apareix a les col·leccions següents

Mostra el registre d'ítem simple