Characterizing fault propagation in safety-critical processor designs
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Projecte de la Comissió EuropeaHigh Performance and Embedded Architecture and Compilation (EC-FP7-287759)
Achieving reduced time-to-market in modern electronic designs targeting safety critical applications is becoming very challenging, as these designs need to go through a certification step that introduces a non-negligible overhead in the verification and validation process. To cope with this challenge, safety-critical systems industry is demanding new tools and methodologies allowing quick and cost-effective means for robustness verification. Microarchitectural simulators have been widely used to test reliability properties in different domains but their use in the process of robustness verification remains yet to be validated against other accepted methods such as RTL or gate-level simulation. In this paper we perform fault injections in an RTL model of a processor to characterize fault propagation. The results and conclusions of this characterization will serve to devise to what extent fault injection methodologies for robustness verification using microarchitectural simulators can be employed.
CitacióEspinosa, Jaime; Hernandez, Carles; Abella, Jaume. Characterizing fault propagation in safety-critical processor designs. A: 21st International On-Line Testing Symposium (IOLTS), 6-8 July 2015, Halkidiki. "2015 IEEE 21st International On-Line Testing Symposium (IOLTS)". Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 144-149.