Increasing multicore system efficiency through intelligent bandwidth shifting
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial
Projecte de la Comissió EuropeaRiding on Moore's Law (EC-FP7-321253)
Memory bandwidth is a crucial resource in computing systems. Current CMP/SMT processors have a significant number of cores and they can run many threads concurrently. This large thread count adds high pressure to the memory bus, which demands high bandwidth to service memory requests from the cores. Hardware data prefetching is a well-known technique for hiding memory latency. Due to its speculative nature, however, in some situations prefetching does not effectively work, wasting memory bandwidth and polluting the caches. Data prefetching efficiency depends on the prefetching algorithm. It also depends on the characteristics of the applications running on the system. In this paper we propose an online bandwidth shifting mechanism that dynamically assigns bandwidth to applications according to their prefetch efficiency. This mechanism maximizes the utilization of memory bandwidth, thereby improving system performance and/or reducing memory power consumption. To the best of our knowledge, this solution is the first to not require hardware support. We evaluate the benefits of using our bandwidth shifting mechanism on a real system - the IBM POWER7. We obtain speedups in the order of 10-20% (in one instance, speedup exceeds 1.6X). Our mechanism does not generate a significant degree of unfairness among the applications. In many cases individual thread performance increases by 10-35%, while virtually no thread experiences a slowdown larger than 5%.
CitacióJiménez, V., Buyuktosunoglu, A., Bose, P., O'Connell, F., Cazorla, F., Valero, M. Increasing multicore system efficiency through intelligent bandwidth shifting. A: International Symposium on High-Performance Computer Architecture. "2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA 2015): Burlingame, California, USA: 7-11 February 2015". San Francisco Bay Area, California: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 39-50.