Interfaces, by nature, are often asynchronous since they serve for
connecting multiple distributed modules/agents without common clock.
However, recent development in theory of asynchronous design in the
area of asynchronous specifications and models, analysis and
verification, synthesis and technology mapping, timing optimization
and performance analysis is not widely known and rarely accepted
The goal of this paper is to fill this gap and to present an
overview of one popular systematic design methodology for design
of asynchronous interface controllers.
This methodology is based on using Petri nets, a formal model that,
from the engineering standpoint, is a formalization of
timing diagrams (waveforms) and from the system designer standpoint is
a concurrent state machine, in which local components can
perform independent or interdependent concurrent actions, changing
their local states asynchronously. We will introduce this model
informally based on a simple example: a VME-bus controller
serving reads from a device to a bus and writes from the bus into the
CitationKishinewsky, M., Cortadella, J., Kondratyev, A., Lavagno, L. "Asynchronous interface specification, analysis and synthesis". 1998.
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