Power-aware voltage tuning for STT-MRAM reliability
Tipus de documentText en actes de congrés
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés restringit per política de l'editorial
One of the most promising emerging memory technologies is the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), due to its high speed, high endurance, low area, low power consumption, and good scaling capability. In this paper, we estimate the STT-MRAM cell reliability under fabrication- and aging-induced process variability, by evaluating its failure probability. We analyze the effect of control voltage tuning on the fresh and aged cell failure probabilities and, as a result, we propose a power- and aging-aware circuit level variability mitigation technique based on control voltage tuning. We observed that increasing the values of control voltages, the cell failure probability is reduced at different extends (according to the control voltage under variation), but also that the power consumption is increased. As a result, we have identified the control voltage with the highest impact on the fresh cell reliability, and on the endurance of the cell under study. Subsequently, by performing a power/reliability trade-off analysis, the appropriate value of this control voltage is determined.
CitacióVatajelu, E., Rodriguez, R., Stefano Di Carlo, Renovell, M., Paolo Prinetto, Figueras, J. Power-aware voltage tuning for STT-MRAM reliability. A: IEEE European Test Symposium. "20th IEEE European test symposium (ETS): proceedings 2015: May 25-29, Cluj-Napoca, Romania". Cluj-Napoca: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 1-6.
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