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RTL synthesis: From logic synthesis to automatic pipelining
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Galcerán Oms, Marc |
dc.contributor.author | Kishinevsky, Mike |
dc.contributor.author | Sapatnekar, Sachin S. |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2016-01-26T10:28:37Z |
dc.date.available | 2016-01-26T10:28:37Z |
dc.date.issued | 2015-11-01 |
dc.identifier.citation | Cortadella, J., Galceran, M., Kishinevsky, M., Sapatnekar, S. RTL synthesis: From logic synthesis to automatic pipelining. "Proceedings of the IEEE", 01 Novembre 2015, vol. 103, núm. 11, p. 2061-2075. |
dc.identifier.issn | 0018-9219 |
dc.identifier.uri | http://hdl.handle.net/2117/82027 |
dc.description.abstract | Design automation has been one of the main propellers of the semiconductor industry with logic synthesis being one of the core technologies in this field. This article reviews the evolution of logic synthesis until the advent of techniques for automatic pipelining based on elastic timing, either synchronous or asynchronous. The emergence of these techniques can enable a productive interaction with tools that can do microarchitectural exploration of complex designs. |
dc.format.extent | 15 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Circuits electrònics |
dc.subject.lcsh | Semiconductor industry |
dc.subject.lcsh | Logic design |
dc.subject.other | Design automation |
dc.subject.other | Logic synthesis |
dc.subject.other | High-level synthesis |
dc.subject.other | Architectural pipelining |
dc.subject.other | Timing elasticity |
dc.title | RTL synthesis: From logic synthesis to automatic pipelining |
dc.type | Article |
dc.subject.lemac | Semiconductors -- Indústria i comerç |
dc.subject.lemac | Estructura lògica |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/JPROC.2015.2456189 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7275092 |
dc.rights.access | Open Access |
local.identifier.drac | 17297173 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2013-46181-C2-1-R/ES/MODELOS Y METODOS COMPUTACIONALES PARA DATOS MASIVOS ESTRUCTURADOS/ |
local.citation.author | Cortadella, J.; Galceran, M.; Kishinevsky, M.; Sapatnekar, S. |
local.citation.publicationName | Proceedings of the IEEE |
local.citation.volume | 103 |
local.citation.number | 11 |
local.citation.startingPage | 2061 |
local.citation.endingPage | 2075 |
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