Elastic cooperative caching: an autonomus dynamically adaptive memory hierarchy for chip multiprocessors
Document typeConference report
PublisherAssociation for Computing Machinery (ACM)
Rights accessRestricted access - publisher's policy
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of applications with very different memory needs, leading to significant optimization opportunities. Existing adaptive memory hierarchies use either centralized structures that limit the scalability or software based resource allocation that increases programming complexity. We propose Elastic Cooperative Caching, a dynamic and scalable memory hierarchy that adapts automatically and autonomously to application behavior for each node. Our configuration uses elastic shared/private caches with fully autonomous and distributed repartitioning units for better scalability. Furthermore, we have extended our elastic configuration with an Adaptive Spilling mechanism to use the shared cache space only when it can produce a performance improvement. Elastic caches allow both the creation of big local private caches for threads with high reuse of private data and the creation of big shared spaces from unused caches. Local data allocation in private regions allows to reduce network usage and efficient cache partitioning allows to reduce off-chip misses. The proposed scheme outperforms previous proposals by a minimum of 12% (on average across the benchmarks) and reduces the number of offchip misses by 16%. Plus, the dynamic and autonomous management of cache resources avoids the reallocation of cache blocks without reuse which results in an increase in energy efficiency of 24%.
CitationHerrero, E.; González, J.; Canal, R. Elastic cooperative caching: an autonomus dynamically adaptive memory hierarchy for chip multiprocessors. A: International Symposium on Computer Architecture. "The 37th Annual International Symposium on Computer Architecture". Saint-Malo: Association for Computing Machinery (ACM), 2010, p. 419-429.